timers: Add support for RZ/N1 SoCs timers

The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.

This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.

This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers

Each timer has its own interrupt, its own prescaler that can be used to device the clock by 25 and all of them can work in either one-shot or

periodic mode.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 drivers/clocksource/Kconfig      |  10 +
 drivers/clocksource/Makefile     |   1 +
 drivers/clocksource/timer-rzn1.c | 442 +++++++++++++++++++++++++++++++
 3 files changed, 453 insertions(+)
 create mode 100644 drivers/clocksource/timer-rzn1.c

drivers/clocksource/Kconfig +0 -0

index d1a33a231a44..f8e49a4ac8f6 100644

drivers/clocksource/Kconfig +7 -0

+       help
+         Enables support for RZ/N1 SoC timers.
+         A timers block in RZ/N1 SoCs is composed of 8 timers
+           - 6 16-bit timers
+           - 2 32-bit timers
+         Two timers blocks are available in RZ/N1 SoCs.
+
 config SUN4I_TIMER
        bool "Sun4i timer driver" if COMPILE_TEST
        depends on HAS_IOMEM

drivers/clocksource/timer-rzn1.c new file +37 -0

+static int rzn1_timer_probe_first(struct platform_device *pdev, struct rzn1_timer *tab_timers,
+                                 void __iomem *base, unsigned long clock_rate)
+{
+       struct device *dev = &pdev->dev;
+       struct rzn1_timer *timer;
+       unsigned int i;
+       char *name;
+       int irq;
+       int ret;
+
+       /*
+        * Probe the first instance. In that case, timers are assigned as
+        * follow:
+        *   - First 16-bit timer: clocksource and sched_clock
+        *   - Other 16-bit timers: clock events for all possible CPUs
+        *   - 32-bit timers: clock events per CPU
+        *
+        * First step, perform all operation that could fail without calling
+        * clockevents_config_and_register(), sched_clock_register() nor
+        * cpuhp_setup_state(). Those operation don't have unregister nor
+        * teardown counterparts and so, once called, we cannot remove the
+        * related resource.
+        */
+
+       /*
+        * First step for 16-bit timers except the first one and all 32-bit
+        * timers.
+        */
+       for (i = RZN1_TIMER_BASE_INDEX_16BIT_TIMERS + 1; i < RZN1_TIMER_NB_TIMERS; i++) {
+               timer = &tab_timers[i];
+
+               rzn1_timer_init(timer, i, base, clock_rate);
+
+               irq = platform_get_irq(pdev, i);
+               if (irq < 0)
+                       return irq;
+

drivers/clocksource/timer-rzn1.c new file +56 -0

+
+               rzn1_timer_int_enable(timer);
+       }
+
+       /*
+        * Second step, almost all operations that can fail have been called.
+        * Timers are ready to work. Start with the last operation that can fail,
+        * installing and invoking hotplug callbacks
+        */
+       rzn1_tab_timers = tab_timers;
+       ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+                               "clockevents/rzn1/global_timer:starting",
+                               rzn1_local_timer_starting_cpu, NULL);
+       if (ret < 0)
+               return dev_err_probe(dev, ret, "Setup CPU hotplug state failed\n");
+
+       /*
+        * At this point, no more operations can fail. Perform remaining
+        * operations. Starting by handling the first 16-bit timer
+        */
+       timer = &tab_timers[RZN1_TIMER_BASE_INDEX_16BIT_TIMERS];
+
+       rzn1_timer_init(timer, RZN1_TIMER_BASE_INDEX_16BIT_TIMERS, base, clock_rate);
+       rzn1_timer_config(timer, GENMASK(timer->width - 1, 0), true);
+
+       rzn1_sched_clock = timer;
+
+       sched_clock_register(rzn1_sched_read, rzn1_sched_clock->width, rzn1_sched_clock->rate);
+
+       rzn1_clocksource.mask = CLOCKSOURCE_MASK(rzn1_sched_clock->width);
+       clocksource_register_hz(&rzn1_clocksource, rzn1_sched_clock->rate);
+
+       /*
+        * Register clockevents only for 16-bit timers. 32-bit timers clockevents
+        * are registered by CPU hotplug startup function set previously by the
+        * cpuhp_setup_state() call.
+        */
+       for (i = RZN1_TIMER_BASE_INDEX_16BIT_TIMERS + 1; i < RZN1_TIMER_NB_16BIT_TIMERS; i++) {
+               timer = &tab_timers[i];
+               clockevents_config_and_register(&timer->ced, timer->rate,
+                                               1, GENMASK(timer->width - 1, 0));
+       }
+
+       return 0;
+}
+
+static int rzn1_timer_probe_other(struct platform_device *pdev, struct rzn1_timer *tab_timers,
+                                 void __iomem *base, unsigned long clock_rate)
+{
+       struct device *dev = &pdev->dev;
+       struct rzn1_timer *timer;
+       unsigned int i;
+       char *name;
+       int irq;
+       int ret;
+

drivers/clocksource/timer-rzn1.c new file +8 -0

+               timer = &tab_timers[i];
+
+               rzn1_timer_init(timer, i, base, clock_rate);
+
+               irq = platform_get_irq(pdev, i);
+               if (irq < 0)
+                       return irq;
+

In the Renesas RZ/N1 SoCs family, two timers block are available.

Each block contains 8 timers composed of 6 16-bits timers and 2 32-bits timers.

Each timer has its own interrupt line.

Describe those timers blocks.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

After contributing the driver, add myself as the maintainer for the Renesas RZ/N1 timers driver.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>