FAILED: patch "[PATCH] perf/x86/intel: Disable PMI for self-reloaded ACR events" failed to apply to 6.18-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 6.18-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.18.y
git checkout FETCH_HEAD
git cherry-pick -x 1271aeccc307066315b2d3b0d5af2510e27018b5
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026051250-afflicted-express-5419@gregkh' --subject-prefix 'PATCH 6.18.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 1271aeccc307066315b2d3b0d5af2510e27018b5 Mon Sep 17 00:00:00 2001
From: Dapeng Mi <[email protected]>
Date: Thu, 30 Apr 2026 08:25:56 +0800
Subject: [PATCH] perf/x86/intel: Disable PMI for self-reloaded ACR events
On platforms with Auto Counter Reload (ACR) support, such as NVL, a "NMI received for unknown reason 30" warning is observed when running multiple events in a group with ACR enabled:
$ perf record -e '{instructions/period=20000,acr_mask=0x2/u,\
cycles/period=40000,acr_mask=0x3/u}' ./testThe warning occurs because the Performance Monitoring Interrupt (PMI) is enabled for the self-reloaded event (the cycles event in this case). According to the Intel SDM, the overflow bit (IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events. Since the bit is not set, the perf NMI handler cannot identify the source of the interrupt, leading to the "unknown reason" message.
Furthermore, enabling PMI for self-reloaded events is unnecessary and can lead to extraneous records that pollute the user's requested data.
Disable the interrupt bit for all events configured with ACR self-reload.
arch/x86/events/intel/core.c +13 -4
@@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_event *event)intel_set_masks (event, idx);/* -* Enable IRQ generation (0x8), if not PEBS, -* and enable ring-3 counting (0x2) and ring-0 counting (0x1) -* if requested: +* Enable IRQ generation (0x8), if not PEBS or self-reloaded +* ACR event, and enable ring-3 counting (0x2) and ring-0 +* counting (0x1) if requested: */ -if (!event->attr.precise_ip) +if (!event->attr.precise_ip && !is_acr_self_reload_event (event)) bits |=INTEL_FIXED_0_ENABLE_PMI ;if (hwc->config &ARCH_PERFMON_EVENTSEL_USR ) bits |=INTEL_FIXED_0_USER ;
@@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event *event)intel_set_masks (event, idx);static_call_cond (intel_pmu_enable_acr_event)(event);static_call_cond (intel_pmu_enable_event_ext)(event); +/* +* For self-reloaded ACR event, don't enable PMI since +* HW won't set overflow bit in GLOBAL_STATUS. Otherwise, +* the PMI would be recognized as a suspicious NMI. +*/ +if (is_acr_self_reload_event (event)) + hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT ; +else if (!event->attr.precise_ip) + hwc->config |=ARCH_PERFMON_EVENTSEL_INT ;__x86_pmu_enable_event (hwc, enable_mask);break ; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
arch/x86/events/perf_event.h +10 -0
@@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_event *event)return check_leader_group (event->group_leader,PERF_X86_EVENT_ACR ); } +static inline bool is_acr_self_reload_event (struct perf_event *event) +{ +struct hw_perf_event *hwc = &event->hw; + +if (hwc->idx <0 ) +return false; + +return test_bit (hwc->idx, (unsigned long *)&hwc->config1); +} +struct amd_nb {int nb_id;/* NorthBridge id */ int refcnt;/* reference count */
Sasha Levin
maintainerPATCH 1/1 perf/x86/intel: Disable PMI for self-reloaded ACR events
From: Dapeng Mi <[email protected]>
[ Upstream commit 1271aeccc307066315b2d3b0d5af2510e27018b5 ]
On platforms with Auto Counter Reload (ACR) support, such as NVL, a "NMI received for unknown reason 30" warning is observed when running multiple events in a group with ACR enabled:
$ perf record -e '{instructions/period=20000,acr_mask=0x2/u,\
cycles/period=40000,acr_mask=0x3/u}' ./testThe warning occurs because the Performance Monitoring Interrupt (PMI) is enabled for the self-reloaded event (the cycles event in this case). According to the Intel SDM, the overflow bit (IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events. Since the bit is not set, the perf NMI handler cannot identify the source of the interrupt, leading to the "unknown reason" message.
Furthermore, enabling PMI for self-reloaded events is unnecessary and can lead to extraneous records that pollute the user's requested data.
Disable the interrupt bit for all events configured with ACR self-reload.
--- arch/x86/events/intel/core.c | 17 +++++++++++++---- arch/x86/events/perf_event.h | 10 ++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-)
arch/x86/events/intel/core.c +13 -4
@@ -2866,11 +2866,11 @@ static void intel_pmu_enable_fixed(struct perf_event *event)intel_set_masks (event, idx);/* -* Enable IRQ generation (0x8), if not PEBS, -* and enable ring-3 counting (0x2) and ring-0 counting (0x1) -* if requested: +* Enable IRQ generation (0x8), if not PEBS or self-reloaded +* ACR event, and enable ring-3 counting (0x2) and ring-0 +* counting (0x1) if requested: */ -if (!event->attr.precise_ip) +if (!event->attr.precise_ip && !is_acr_self_reload_event (event)) bits |=INTEL_FIXED_0_ENABLE_PMI ;if (hwc->config &ARCH_PERFMON_EVENTSEL_USR ) bits |=INTEL_FIXED_0_USER ;
@@ -2955,6 +2955,15 @@ static void intel_pmu_enable_event(struct perf_event *event) enable_mask |=ARCH_PERFMON_EVENTSEL_BR_CNTR ;intel_set_masks (event, idx);static_call_cond (intel_pmu_enable_acr_event)(event); +/* +* For self-reloaded ACR event, don't enable PMI since +* HW won't set overflow bit in GLOBAL_STATUS. Otherwise, +* the PMI would be recognized as a suspicious NMI. +*/ +if (is_acr_self_reload_event (event)) + hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT ; +else if (!event->attr.precise_ip) + hwc->config |=ARCH_PERFMON_EVENTSEL_INT ;__x86_pmu_enable_event (hwc, enable_mask);break ; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
arch/x86/events/perf_event.h +10 -0
@@ -133,6 +133,16 @@ static inline bool is_acr_event_group(struct perf_event *event)return check_leader_group (event->group_leader,PERF_X86_EVENT_ACR ); } +static inline bool is_acr_self_reload_event (struct perf_event *event) +{ +struct hw_perf_event *hwc = &event->hw; + +if (hwc->idx <0 ) +return false; + +return test_bit (hwc->idx, (unsigned long *)&hwc->config1); +} +struct amd_nb {int nb_id;/* NorthBridge id */ int refcnt;/* reference count */
Signature · 1 line
2.53.0