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Add WorldGuard hwiso support

PATCH In review Raymond Mao 2 participants 12 messages May 19 – Jul 25 1 message not in the archive RISC-V

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cover Add WorldGuard hwiso support

From: Raymond Mao <[email protected]>

This series adds WorldGuard implementation for OpenSBI on top of the generic hardware isolation (HWISO) hooks.

The goal is to let OpenSBI:
- program platform WorldGuard checker state at boot
- parse per-domain WorldGuard metadata from the device tree
- reprogram hart WorldGuard runtime state during domain transitions

The current implementation targets the WorldGuard model of sifive,wgchecker2 checker plus per-hart and per-domain WorldGuard metadata from DT.

The series is organized as follows:
1. add the WorldGuard CSR definitions and hart extension flags needed to detect support for MLWID, MWIDDELEG, and SLWID
2. document the HWISO / WorldGuard device-tree metadata used by the current implementation
3. add a QEMU virt DT overlay that describes domain WID/WID list assignment and checker permission policy for the current test flow
4. add generic-platform WorldGuard runtime support together with wgchecker2 checker parsing and boot-time MMIO programming
5. add generic HWISO SBIUNIT coverage
6. add QEMU virt WorldGuard mechanism-specific SBIUNIT checks for boot-time checker programming and runtime CSR state
7. add a QEMU virt failure-mode SBIUNIT test that intentionally triggers a denied WorldGuard access and verifies the expected trap

Notes:
- The implementation has been verified with QEMU virt that supports wg=on[1].
- This series depends on previous patches ([2] and [3]) for introducing HWISO framework.

[1] https://github.com/cwshu/qemu/tree/riscv-wg-dts
[2] [PATCH 1/2] sbi: add hardware isolation abstraction framework

    https://lore.kernel.org/opensbi/[email protected]/
[3] [PATCH 2/2] sbi: route domain lifecycle transitions through hwiso hooks
    https://lore.kernel.org/opensbi/[email protected]/

Raymond Mao (7):
hart: add WorldGuard CSR IDs and hart extension flags
docs: document hwiso WorldGuard DT bindings [NOT-FOR-UPSTREAM] platform: virt: add QEMU WorldGuard hwiso overlay
platform: generic: add WorldGuard hwiso support with wgchecker2
test: add generic hwiso SBI unit coverage
platform: virt: add QEMU virt WorldGuard hwiso tests
platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

 docs/domain_support.md                        | 159 +++++
 include/sbi/riscv_encoding.h                  |   3 +
 include/sbi/sbi_hart.h                        |   4 +
 include/sbi/sbi_hwiso_test.h                  |  35 ++
 lib/sbi/objects.mk                            |   3 +
 lib/sbi/sbi_hart.c                            |   2 +
 lib/sbi/sbi_hwiso_test.c                      | 173 ++++++
 lib/sbi/sbi_hwiso_testlib.c                   | 119 ++++
 platform/generic/include/wgchecker2.h         |  55 ++
 platform/generic/include/worldguard.h         |  45 ++
 platform/generic/objects.mk                   |   4 +
 platform/generic/platform.c                   |  11 +
 .../generic/virt/qemu-virt-hwiso-overlay.dts  | 121 ++++
 .../generic/virt/qemu_virt_wgchecker_test.c   | 356 +++++++++++
 platform/generic/virt/qemu_virt_worldguard.c  |  42 ++
 platform/generic/wgchecker2.c                 | 585 ++++++++++++++++++
 platform/generic/worldguard.c                 | 522 ++++++++++++++++
 17 files changed, 2239 insertions(+)
 create mode 100644 include/sbi/sbi_hwiso_test.h
 create mode 100644 lib/sbi/sbi_hwiso_test.c
 create mode 100644 lib/sbi/sbi_hwiso_testlib.c
 create mode 100644 platform/generic/include/wgchecker2.h
 create mode 100644 platform/generic/include/worldguard.h
 create mode 100644 platform/generic/virt/qemu-virt-hwiso-overlay.dts
 create mode 100644 platform/generic/virt/qemu_virt_wgchecker_test.c
 create mode 100644 platform/generic/virt/qemu_virt_worldguard.c
 create mode 100644 platform/generic/wgchecker2.c
 create mode 100644 platform/generic/worldguard.c
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#1 lore raw

PATCH 1/7 hart: add WorldGuard CSR IDs and hart extension flags

From: Raymond Mao <[email protected]>

Define the WorldGuard-related CSR numbers and claim smwg / sswg hart extensions so platform code can probe support before programming MLWID, MWIDDELEG and SLWID.

---
 include/sbi/riscv_encoding.h | 3 +++
 include/sbi/sbi_hart.h       | 4 ++++
 lib/sbi/sbi_hart.c           | 2 ++
 3 files changed, 9 insertions(+)
include/sbi/riscv_encoding.h +3 -0
index 46bbeed0..48304132 100644
@@ -331,6 +331,7 @@
 
 /* Supervisor Protection and Translation */
 #define CSR_SATP			0x180
+#define CSR_SLWID			0x190
 
 /* Supervisor Indirect Register Alias */
 #define CSR_SISELECT			0x150
@@ -454,6 +455,7 @@
 /* Machine Configuration */
 #define CSR_MENVCFG			0x30a
 #define CSR_MENVCFGH			0x31a
+#define CSR_MLWID			0x390
 
 /* Machine Trap Handling */
 #define CSR_MSCRATCH			0x340
@@ -680,6 +682,7 @@
 /* Machine Security Configuration CSR (mseccfg) */
 #define CSR_MSECCFG			0x747
 #define CSR_MSECCFGH			0x757
+#define CSR_MWIDDELEG			0x748
 
 #define MSECCFG_MML_SHIFT		(0)
 #define MSECCFG_MML			(_UL(1) << MSECCFG_MML_SHIFT)
include/sbi/sbi_hart.h +4 -0
index cc78eec6..2c725ae2 100644
@@ -63,6 +63,10 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_SSCSRIND,
 	/** Hart has Ssccfg extension */
 	SBI_HART_EXT_SSCCFG,
+	/** Hart has Smwg extension */
+	SBI_HART_EXT_SMWG,
+	/** Hart has Sswg extension */
+	SBI_HART_EXT_SSWG,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
lib/sbi/sbi_hart.c +2 -0
index 3d136944..6fc03a59 100644
@@ -666,6 +666,8 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
 	__SBI_HART_EXT_DATA(sdtrig, SBI_HART_EXT_SDTRIG),
 	__SBI_HART_EXT_DATA(smcsrind, SBI_HART_EXT_SMCSRIND),
 	__SBI_HART_EXT_DATA(smcdeleg, SBI_HART_EXT_SMCDELEG),
+	__SBI_HART_EXT_DATA(smwg, SBI_HART_EXT_SMWG),
+	__SBI_HART_EXT_DATA(sswg, SBI_HART_EXT_SSWG),
 };
 
 /**
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#2 lore raw

PATCH 2/7 docs: document hwiso WorldGuard DT bindings

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Document the hw-isolation and worldguard_cfg device-tree metadata used by the HWISO framework for WorldGuard-enabled platforms.

---
 docs/domain_support.md | 159 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 159 insertions(+)
docs/domain_support.md +159 -0
index b34e43aa..d81f1bc6 100644
@@ -201,6 +201,165 @@ The DT properties of a domain instance DT node are as follows:
   whether the domain instance is allowed to do system reset.
 * **system-suspend-allowed** (Optional) - A boolean flag representing
   whether the domain instance is allowed to do system suspend.
+* **hw-isolation** (Optional) - A child node acting as a container for
+  system-level hardware isolation mechanisms. Each child node represents a
+  single mechanism configured via its compatible string and properties.
+
+Hardware Isolation Hooks
+------------------------
+
+OpenSBI provides a system-level hardware isolation framework that dispatches
+all registered mechanisms in the following phases:
+
+* **init** - Runs at boot to configure system-level isolation features.
+* **domain_init** - Parses per-domain isolation configuration.
+* **domain_exit** - Runs before switching out of a domain.
+* **domain_enter** - Runs after switching into a domain.
+
+Hardware Isolation Device Tree Binding
+--------------------------------------
+
+The hardware isolation configuration is specified as an optional child node
+named **hw-isolation** under a domain instance node. The **hw-isolation**
+node is a container for one or more mechanism nodes.
+
+The DT properties of a hardware isolation container node are as follows:
+
+* **#address-cells** / **#size-cells** (Optional) - Standard container node
+  properties. They are not interpreted by OpenSBI.
+
+Each hardware isolation mechanism has its own properties and compatible
+string. A mechanism can either use per-domain properties below the domain
+instance node, or parse system-level DT nodes describing isolation hardware.
+
+For the WorldGuard support on QEMU virt, OpenSBI parses the
+following WG-style system nodes:
+
+* **sifive,wgchecker2** - WorldGuard checker node.
+* **reg** - Checker MMIO base/size.
+* **sifive,slot-count** - Number of hardware checker slots.
+* **sifive,subordinates** - List of protected resource phandles owned by the
+  checker.
+* **worldguard_cfg** - Child node of a protected memory or device node
+  describing WorldGuard policy for that resource.
+* **perms** - 64-bit permission bitmap values encoded as **<hi lo>** cell
+  pairs, with either one value for the whole resource or one value per
+  protected range.
+* **reg** - Optional protected address ranges inside a **worldguard_cfg**
+  child. If omitted, the resource node's own **reg** is used. A single
+  subordinate with one **perms** entry and no explicit **worldguard_cfg/reg**
+  is treated as a full-checker rule.
+* **worldguard** - Optional CPU child node compatible with **riscv,wgcpu**
+  providing default WG execution state.
+* **mwid** - Default machine world ID for a hart.
+* **mwidlist** - Valid/delegable world IDs for that hart.
+
+Domain nodes can optionally provide WG execution metadata under the
+**hw-isolation** container:
+
+* **worldguard,wid** - Machine world ID selected when entering the domain.
+* **worldguard,widlist** - World IDs delegated to the domain.
+
+At runtime the WorldGuard implementation uses the hooks as follows:
+
+* **init** - Parses all WG checker nodes, validates the protected ranges, and
+  programs checker MMIO slots at boot when platform checker nodes are
+  present. Runtime WID/WID list support is enabled only when per-CPU WG
+  runtime nodes are present; checker-only DTs do not force runtime
+  switching on.
+* **domain_init** - Parses per-domain **worldguard,wid** and
+  **worldguard,widlist** metadata.
+* **domain_exit** - Quiesces the current hart back to its per-hart default
+  machine WID and clears **MWIDDELEG** before the handoff.
+* **domain_enter** - Reprograms **MLWID**, **MWIDDELEG**, and, when
+  delegation is active, **SLWID** for the destination domain when the hart
+  supports **smwg** / **sswg**.
+
+The CPU **worldguard** defaults are parsed per hart from **/cpus/<cpu>**, so
+platforms may provide different default **mwid** / **mwidlist** values on
+different harts.
+
+Hardware Isolation Examples
+---------------------------
+
+Domain instance with WG execution metadata:
+
+```text
+    chosen {
+        opensbi-domains {
+            compatible = "opensbi,domain,config";
+
+            example_domain: domain@1 {
+                compatible = "opensbi,domain,instance";
+                possible-harts = <&cpu2>;
+                regions = <&mem0 0x3f>;
+                boot-hart = <&cpu2>;
+                next-addr = <0x00000000 0x80200000>;
+                next-mode = <0x1>;
+
+                hw-isolation {
+                    worldguard {
+                        compatible = "sifive,wgchecker2";
+                        worldguard,wid = <1>;
+                        worldguard,widlist = <1 3>;
+                    };
+                };
+            };
+        };
+    };
+```
+
+WG checker, CPU default state, and protected resource example. These nodes
+remain in the normal system DT topology because they describe isolation
+hardware and protected resources, not OpenSBI domain instances:
+
+```text
+    cpu0: cpu@0 {
+        worldguard {
+            compatible = "riscv,wgcpu";
+            mwid = <0>;
+            mwidlist = <0 1 3>;
+        };
+    };
+
+    flash0: flash@20000000 {
+        reg = <0x0 0x20000000 0x0 0x2000000>;
+        worldguard_cfg {
+            perms = <0x0 0xc3>;
+        };
+    };
+
+    uart0: serial@10000000 {
+        reg = <0x0 0x10000000 0x0 0x100>;
+        worldguard_cfg {
+            perms = <0x0 0xc0>;
+        };
+    };
+
+    memory0: memory@80000000 {
+        reg = <0x0 0x80000000 0x0 0x80000000>;
+        worldguard_cfg {
+            reg = <0x0 0x80000000 0x0 0x40000000
+                   0x0 0xc0000000 0x0 0x01000000
+                   0x0 0xc1000000 0x0 0x3f000000>;
+            perms = <0x0 0xcf 0x0 0xcc 0x0 0xcf>;
+        };
+    };
+
+    wgchecker0: wgchecker@10100000 {
+        compatible = "sifive,wgchecker2";
+        reg = <0x0 0x10100000 0x0 0x1000>;
+        sifive,slot-count = <8>;
+        sifive,subordinates = <&memory0 &flash0 &uart0>;
+    };
+```
+
+The test overlay used in this tree is at:
+
+* **platform/generic/virt/qemu-virt-hwiso-overlay.dts**
+
+That overlay only adds per-domain and per-resource metadata. The base DTB
+must still provide the WG checker nodes and per-CPU **worldguard** nodes.
 
 ### Assigning HART To Domain Instance
 
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#3 lore raw

PATCH 3/7 platform: virt: add QEMU WorldGuard hwiso overlay

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Add a QEMU virt device-tree overlay that describes OpenSBI domain WorldGuard metadata and checker permission policy for the current HWISO test and demo flow.

---
 .../generic/virt/qemu-virt-hwiso-overlay.dts  | 121 ++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 platform/generic/virt/qemu-virt-hwiso-overlay.dts
platform/generic/virt/qemu-virt-hwiso-overlay.dts new file +121 -0
new file mode 100644
index 00000000..e44d85b7
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/dts-v1/;
+/plugin/;
+
+/*
+ * Test-only overlay for exercising HWISO with WorldGuard metadata.
+ *
+ * This overlay only adds OpenSBI domain metadata and worldguard_cfg resource
+ * policy. The base DTB is expected to already provide the WG checker nodes
+ * and per-CPU worldguard child nodes.
+ *
+ * Usage:
+ * Domain hart phandles are filled in after merge because fdtoverlay does not
+ * reliably resolve CPU-node references against QEMU dumpdtb output here.
+ * See below steps for filling the domain hart phandles (assume the dumped dtb
+ * and merged dtb are represented by 'qemu.dtb' and 'qemu-merged.dtb'
+ * respectively):
+ *   cpu0_phandle=$(fdtget -t x qemu.dtb /cpus/cpu@0 phandle)
+ *   cpu1_phandle=$(fdtget -t x qemu.dtb /cpus/cpu@1 phandle)
+ *   fdtput -t x qemu-merged.dtb /chosen/opensbi-domains/domain@0 \
+ *     possible-harts "$cpu0_phandle" "$cpu1_phandle"
+ *   fdtput -t x qemu-merged.dtb /chosen/opensbi-domains/domain@0 \
+ *     boot-hart "$cpu0_phandle"
+ *   fdtput -t x qemu-merged.dtb /chosen/opensbi-domains/domain@1 \
+ *     possible-harts "$cpu1_phandle"
+ *   fdtput -t x qemu-merged.dtb /chosen/opensbi-domains/domain@1 \
+ *     boot-hart "$cpu1_phandle"
+ */
+/ {
+	fragment@0 {
+		target-path = "/chosen";
+		__overlay__ {
+			opensbi-domains {
+				compatible = "opensbi,domain,config";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				memregion0: memregion@0 {
+					compatible = "opensbi,domain,memregion";
+					base = <0x00000000 0x80000000>;
+					order = <0x1f>;
+				};
+
+				guest0: domain@0 {
+					compatible = "opensbi,domain,instance";
+					regions = <&memregion0 0x3f>;
+					next-addr = <0x00000000 0x80200000>;
+					next-arg1 = <0x00000000 0x82200000>;
+					next-mode = <0x1>;
+
+					hw-isolation {
+						worldguard {
+							compatible = "sifive,wgchecker2";
+							worldguard,wid = <0>;
+							worldguard,widlist = <0 1 3>;
+						};
+					};
+				};
+
+				guest1: domain@1 {
+					compatible = "opensbi,domain,instance";
+					regions = <&memregion0 0x3f>;
+					next-addr = <0x00000000 0x80200000>;
+					next-mode = <0x1>;
+
+					hw-isolation {
+						worldguard {
+							compatible = "sifive,wgchecker2";
+							worldguard,wid = <1>;
+							worldguard,widlist = <1 3>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/cpus/cpu@0";
+		__overlay__ {
+			opensbi-domain = <&guest0>;
+		};
+	};
+
+	fragment@2 {
+		target-path = "/cpus/cpu@1";
+		__overlay__ {
+			opensbi-domain = <&guest0>;
+		};
+	};
+
+	fragment@3 {
+		target-path = "/memory@80000000";
+		__overlay__ {
+			worldguard_cfg {
+				reg = <0x00000000 0x80000000 0x00000000 0x40000000
+				       0x00000000 0xc0000000 0x00000000 0x01000000
+				       0x00000000 0xc1000000 0x00000000 0x3f000000>;
+				perms = <0x0 0xcf 0x0 0xcc 0x0 0xcf>;
+			};
+		};
+	};
+
+	fragment@4 {
+		target-path = "/flash@20000000";
+		__overlay__ {
+			worldguard_cfg {
+				perms = <0x0 0xc3>;
+			};
+		};
+	};
+
+	fragment@5 {
+		target-path = "/soc/serial@10000000";
+		__overlay__ {
+			worldguard_cfg {
+				perms = <0x0 0xc0>;
+			};
+		};
+	};
+};
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#4 lore raw

PATCH 4/7 platform: generic: add WorldGuard hwiso support with wgchecker2

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Add WorldGuard support for the hardware isolation framework on the generic platform.

Implement boot-time parsing of sifive,wgchecker2 checker instances and their subordinate resource permissions from the FDT, then program the checker MMIO state according to the worldguard_cfg rules described for each protected resource.

Add WorldGuard runtime support to parse per-hart CPU defaults and per-domain WorldGuard metadata, and use that state to reprogram MLWID, MWIDDELEG, and SLWID during domain transitions.

Keep the QEMU virt platform code as the integration layer that registers the WorldGuard hardware isolation mechanism for the virt platform.

---
 platform/generic/include/wgchecker2.h        |  55 ++
 platform/generic/include/worldguard.h        |  45 ++
 platform/generic/objects.mk                  |   3 +
 platform/generic/platform.c                  |  11 +
 platform/generic/virt/qemu_virt_worldguard.c |  42 ++
 platform/generic/wgchecker2.c                | 585 +++++++++++++++++++
 platform/generic/worldguard.c                | 522 +++++++++++++++++
 7 files changed, 1263 insertions(+)
 create mode 100644 platform/generic/include/wgchecker2.h
 create mode 100644 platform/generic/include/worldguard.h
 create mode 100644 platform/generic/virt/qemu_virt_worldguard.c
 create mode 100644 platform/generic/wgchecker2.c
 create mode 100644 platform/generic/worldguard.c
platform/generic/include/wgchecker2.h new file +55 -0
new file mode 100644
index 00000000..37b4bfe0
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026 RISCstar Solutions Corporation.
+ *
+ * Author: Raymond Mao <[email protected]>
+ */
+
+#ifndef __PLATFORM_GENERIC_WGCHECKER2_H__
+#define __PLATFORM_GENERIC_WGCHECKER2_H__
+
+#include <sbi/sbi_types.h>
+
+#define WGCHECKER2_COMPAT			"sifive,wgchecker2"
+#define WGCHECKER2_CFG_NODE			"worldguard_cfg"
+
+#define WGCHECKER2_PROP_SLOT_COUNT		"sifive,slot-count"
+#define WGCHECKER2_PROP_SUBORDINATES		"sifive,subordinates"
+#define WGCHECKER2_PROP_PERMS			"perms"
+
+/*
+ * The current wgchecker2 model uses a 64-bit permission register with
+ * 2 bits per world, so the current checker model tracks at most 32 WIDs.
+ */
+#define WGCHECKER2_MAX_WIDS			32
+
+/* The current wgchecker2 model requires 4 KiB slot alignment. */
+#define WGCHECKER2_MIN_ALIGN			0x1000ULL
+
+/* Current wgchecker2 MMIO register layout. */
+#define WGCHECKER2_MMIO_NSLOTS			0x008
+#define WGCHECKER2_MMIO_ERRCAUSE		0x010
+#define WGCHECKER2_MMIO_ERRADDR			0x018
+#define WGCHECKER2_MMIO_SLOT_BASE		0x020
+#define WGCHECKER2_MMIO_SLOT_STRIDE		0x020
+#define WGCHECKER2_MMIO_SLOT_ADDR		0x000
+#define WGCHECKER2_MMIO_SLOT_PERM		0x008
+#define WGCHECKER2_MMIO_SLOT_CFG		0x010
+
+/* Current wgchecker2 slot cfg.A[1:0] encoding. */
+#define WGCHECKER2_SLOT_CFG_A_MASK		0x3
+#define WGCHECKER2_SLOT_CFG_A_OFF		0x0
+#define WGCHECKER2_SLOT_CFG_A_TOR		0x1
+
+struct wgchecker2_range {
+	u64 base;
+	u64 size;
+	u64 perm;
+};
+
+u32 wgchecker2_count_platform_checkers(void *fdt);
+int wgchecker2_init(void *fdt);
+void wgchecker2_cleanup(void);
+u32 wgchecker2_checker_count(void);
+
+#endif
platform/generic/include/worldguard.h new file +45 -0

45 lines not on this page · raw message

platform/generic/objects.mk +3 -0
index 85aa723a..80bd65ea 100644
@@ -20,6 +20,9 @@ platform-runcmd = qemu-system-riscv$(PLATFORM_RISCV_XLEN) -M virt -m 256M \
 # Objects to build
 platform-objs-y += platform.o
 platform-objs-y += platform_override_modules.o
+platform-objs-y += worldguard.o
+platform-objs-y += wgchecker2.o
+platform-objs-y += virt/qemu_virt_worldguard.o
 
 # Blobs to build
 FW_TEXT_START=0x80000000
platform/generic/platform.c +11 -0
index b76c2a2f..7326b709 100644
@@ -11,6 +11,7 @@
 #include <platform_override.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/sbi_bitops.h>
+#include <sbi/sbi_error.h>
 #include <sbi/sbi_hartmask.h>
 #include <sbi/sbi_heap.h>
 #include <sbi/sbi_platform.h>
@@ -30,6 +31,8 @@
 #include <sbi_utils/rpxy/fdt_rpxy.h>
 #include <sbi_utils/serial/semihosting.h>
 
+extern int qemu_virt_worldguard_register(void *fdt);
+
 /* List of platform override modules generated at compile time */
 extern const struct platform_override *platform_override_modules[];
 extern unsigned long platform_override_modules_size;
@@ -222,9 +225,17 @@ static int generic_nascent_init(void)
 
 static int generic_early_init(bool cold_boot)
 {
+	int rc;
+
 	if (cold_boot)
 		fdt_reset_init();
 
+	if (cold_boot) {
+		rc = qemu_virt_worldguard_register(fdt_get_address());
+		if (rc && rc != SBI_EALREADY)
+			return rc;
+	}
+
 	if (!generic_plat || !generic_plat->early_init)
 		return 0;
 
platform/generic/virt/qemu_virt_worldguard.c new file +42 -0

42 lines not on this page · raw message

platform/generic/wgchecker2.c new file +585 -0

585 lines not on this page · raw message

platform/generic/worldguard.c new file +522 -0

522 lines not on this page · raw message

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#5 lore raw

PATCH 5/7 test: add generic hwiso SBI unit coverage

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Add a generic HWISO SBI unit suite that exercises boot-time initialization and domain-switch hook sequencing without embedding one platform mechanism's policy directly into the core test driver.

Provide a small test registration layer so each HWISO mechanism can supply its own state and quiesce assertions.

---
 include/sbi/sbi_hwiso_test.h |  33 +++++++
 lib/sbi/objects.mk           |   3 +
 lib/sbi/sbi_hwiso_test.c     | 167 +++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_hwiso_testlib.c  | 108 ++++++++++++++++++++++
 4 files changed, 311 insertions(+)
 create mode 100644 include/sbi/sbi_hwiso_test.h
 create mode 100644 lib/sbi/sbi_hwiso_test.c
 create mode 100644 lib/sbi/sbi_hwiso_testlib.c
include/sbi/sbi_hwiso_test.h new file +33 -0
new file mode 100644
index 00000000..3970df5a
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026 RISCstar Solutions Corporation.
+ *
+ * Author: Raymond Mao <[email protected]>
+ */
+
+#ifndef __SBI_HWISO_TEST_H__
+#define __SBI_HWISO_TEST_H__
+
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_hwiso.h>
+#include <sbi/sbi_unit_test.h>
+
+#ifdef CONFIG_SBIUNIT
+struct sbi_hwiso_test_ops {
+	void (*boot_test)(struct sbiunit_test_case *test);
+	void (*domain_state_test)(struct sbiunit_test_case *test,
+				 const struct sbi_domain *dom, void *ctx);
+	void (*domain_quiesce_test)(struct sbiunit_test_case *test,
+				    const struct sbi_domain *dom, void *ctx);
+};
+
+int sbi_hwiso_test_register(const struct sbi_hwiso_ops *ops,
+			    const struct sbi_hwiso_test_ops *test_ops);
+void sbi_hwiso_test_boot(struct sbiunit_test_case *test);
+void sbi_hwiso_test_domain_state(struct sbiunit_test_case *test,
+				 const struct sbi_domain *dom);
+void sbi_hwiso_test_domain_quiesced(struct sbiunit_test_case *test,
+				    const struct sbi_domain *dom);
+#endif
+
+#endif
lib/sbi/objects.mk +3 -0
index 6091499a..8839d13c 100644
@@ -13,9 +13,12 @@ libsbi-objs-y += riscv_hardfp.o
 libsbi-objs-y += riscv_locks.o
 libsbi-objs-$(CONFIG_SBIUNIT) += sbi_unit_test.o
 libsbi-objs-$(CONFIG_SBIUNIT) += sbi_unit_tests.o
+libsbi-objs-$(CONFIG_SBIUNIT) += sbi_hwiso_testlib.o
 
 libsbi-objs-$(CONFIG_SBIUNIT) += sbi_bitmap_test.o
+libsbi-objs-$(CONFIG_SBIUNIT) += sbi_hwiso_test.o
 carray-sbi_unit_tests-$(CONFIG_SBIUNIT) += bitmap_test_suite
+carray-sbi_unit_tests-$(CONFIG_SBIUNIT) += hwiso_test_suite
 carray-sbi_unit_tests-$(CONFIG_SBIUNIT) += console_test_suite
 
 libsbi-objs-y += sbi_ecall.o
lib/sbi/sbi_hwiso_test.c new file +167 -0

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lib/sbi/sbi_hwiso_testlib.c new file +108 -0

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#6 lore raw

PATCH 6/7 platform: virt: add QEMU virt WorldGuard hwiso tests

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Add QEMU virt WorldGuard mechanism-specific tests for boot-time checker programming and runtime CSR state, and verify the expected root / domain@0 / domain@1 behavior through the HWISO test callback API.

---
 platform/generic/objects.mk                   |   1 +
 .../generic/virt/qemu_virt_wgchecker_test.c   | 321 ++++++++++++++++++
 2 files changed, 322 insertions(+)
 create mode 100644 platform/generic/virt/qemu_virt_wgchecker_test.c
platform/generic/objects.mk +1 -0
index 80bd65ea..be58873a 100644
@@ -23,6 +23,7 @@ platform-objs-y += platform_override_modules.o
 platform-objs-y += worldguard.o
 platform-objs-y += wgchecker2.o
 platform-objs-y += virt/qemu_virt_worldguard.o
+platform-objs-$(CONFIG_SBIUNIT) += virt/qemu_virt_wgchecker_test.o
 
 # Blobs to build
 FW_TEXT_START=0x80000000
platform/generic/virt/qemu_virt_wgchecker_test.c new file +321 -0

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#7 lore raw

PATCH 7/7 platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

In reply to Raymond Mao

From: Raymond Mao <[email protected]>

Extend the generic HWISO SBIUNIT test hook interface with a failure-test callback and invoke it from a new hwiso_failure_mode_test case.

Implement the QEMU virt WorldGuard failure-mode test by switching into domain@0's WorldGuard state, issuing an intentional denied store to a protected DRAM address, and verifying that the access raises the expected store access fault with the faulting address recorded in tval.
Also print the captured trap cause and trap value so the negative-path result is visible in the runtime log.

---
 include/sbi/sbi_hwiso_test.h                  |  2 ++
 lib/sbi/sbi_hwiso_test.c                      |  6 ++++
 lib/sbi/sbi_hwiso_testlib.c                   | 11 ++++++
 .../generic/virt/qemu_virt_wgchecker_test.c   | 35 +++++++++++++++++++
 4 files changed, 54 insertions(+)
include/sbi/sbi_hwiso_test.h +2 -0
index 3970df5a..354e8d17 100644
@@ -15,6 +15,7 @@
 #ifdef CONFIG_SBIUNIT
 struct sbi_hwiso_test_ops {
 	void (*boot_test)(struct sbiunit_test_case *test);
+	void (*failure_test)(struct sbiunit_test_case *test);
 	void (*domain_state_test)(struct sbiunit_test_case *test,
 				 const struct sbi_domain *dom, void *ctx);
 	void (*domain_quiesce_test)(struct sbiunit_test_case *test,
@@ -24,6 +25,7 @@ struct sbi_hwiso_test_ops {
 int sbi_hwiso_test_register(const struct sbi_hwiso_ops *ops,
 			    const struct sbi_hwiso_test_ops *test_ops);
 void sbi_hwiso_test_boot(struct sbiunit_test_case *test);
+void sbi_hwiso_test_failure(struct sbiunit_test_case *test);
 void sbi_hwiso_test_domain_state(struct sbiunit_test_case *test,
 				 const struct sbi_domain *dom);
 void sbi_hwiso_test_domain_quiesced(struct sbiunit_test_case *test,
lib/sbi/sbi_hwiso_test.c +6 -0
index 716596e2..6b8384d4 100644
@@ -96,6 +96,11 @@ static void hwiso_boot_test(struct sbiunit_test_case *test)
 	sbi_hwiso_test_boot(test);
 }
 
+static void hwiso_failure_mode_test(struct sbiunit_test_case *test)
+{
+	sbi_hwiso_test_failure(test);
+}
+
 static void hwiso_domain_switch_test(struct sbiunit_test_case *test)
 {
 	struct sbi_domain *cur_dom = sbi_domain_thishart_ptr();
@@ -160,6 +165,7 @@ out:
 
 static struct sbiunit_test_case hwiso_test_cases[] = {
 	SBIUNIT_TEST_CASE(hwiso_boot_test),
+	SBIUNIT_TEST_CASE(hwiso_failure_mode_test),
 	SBIUNIT_TEST_CASE(hwiso_domain_switch_test),
 	SBIUNIT_END_CASE,
 };
lib/sbi/sbi_hwiso_testlib.c +11 -0
index 2a988088..2dfb8646 100644
@@ -64,6 +64,17 @@ void sbi_hwiso_test_boot(struct sbiunit_test_case *test)
 	}
 }
 
+void sbi_hwiso_test_failure(struct sbiunit_test_case *test)
+{
+	struct sbi_hwiso_test_node *entry;
+
+	sbi_list_for_each_entry(entry, &hwiso_test_ops_list, node) {
+		if (!entry->test_ops->failure_test)
+			continue;
+		entry->test_ops->failure_test(test);
+	}
+}
+
 void sbi_hwiso_test_domain_state(struct sbiunit_test_case *test,
 				 const struct sbi_domain *dom)
 {
platform/generic/virt/qemu_virt_wgchecker_test.c +35 -0
index 0eeaa3a0..eaaa39f7 100644
@@ -7,14 +7,17 @@
 #include <libfdt.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
 #include <sbi/sbi_domain.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_hwiso.h>
 #include <sbi/sbi_hwiso_test.h>
 #include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_unit_test.h>
+#include <sbi/sbi_unpriv.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <wgchecker2.h>
 #include <worldguard.h>
@@ -40,6 +43,8 @@ struct qemu_virt_wg_expect {
 	u32 slwid;
 };
 
+#define QEMU_VIRT_WG_DENIED_STORE_ADDR		0xc0001000UL
+
 static u64 qemu_virt_wg_mmio_read64(unsigned long addr)
 {
 #if __riscv_xlen != 32
@@ -314,8 +319,38 @@ static void qemu_virt_wg_boot_test(struct sbiunit_test_case *test)
 			  0);
 }
 
+static void qemu_virt_wg_failure_test(struct sbiunit_test_case *test)
+{
+	struct sbi_domain *cur_dom = sbi_domain_thishart_ptr();
+	struct sbi_domain *dom0 = qemu_virt_wg_find_domain("domain@0");
+	struct sbi_trap_info trap = { 0 };
+
+	SBIUNIT_ASSERT_NE(test, cur_dom, NULL);
+	SBIUNIT_ASSERT_NE(test, dom0, NULL);
+
+	if (cur_dom != dom0) {
+		sbi_hwiso_domain_exit(cur_dom, dom0);
+		sbi_hwiso_domain_enter(dom0, cur_dom);
+	}
+
+	sbi_store_u32((u32 *)QEMU_VIRT_WG_DENIED_STORE_ADDR, 0x5a5aa5a5U,
+		      &trap);
+
+	if (cur_dom != dom0) {
+		sbi_hwiso_domain_exit(dom0, cur_dom);
+		sbi_hwiso_domain_enter(cur_dom, dom0);
+	}
+
+	sbi_printf("[WG TEST] failure trap cause=0x%lx tval=0x%lx\n",
+		   trap.cause, trap.tval);
+
+	SBIUNIT_ASSERT_EQ(test, trap.cause, CAUSE_STORE_ACCESS);
+	SBIUNIT_ASSERT_EQ(test, trap.tval, QEMU_VIRT_WG_DENIED_STORE_ADDR);
+}
+
 const struct sbi_hwiso_test_ops qemu_virt_worldguard_test_ops = {
 	.boot_test = qemu_virt_wg_boot_test,
+	.failure_test = qemu_virt_wg_failure_test,
 	.domain_state_test = qemu_virt_wg_assert_state,
 	.domain_quiesce_test = qemu_virt_wg_assert_quiesced,
 };
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#8 lore raw
In reply to Raymond Mao
Quoted 42 lines · Raymond Mao

From: Raymond Mao <[email protected]>

This series adds WorldGuard implementation for OpenSBI on top of the generic hardware isolation (HWISO) hooks.

The goal is to let OpenSBI:
- program platform WorldGuard checker state at boot
- parse per-domain WorldGuard metadata from the device tree
- reprogram hart WorldGuard runtime state during domain transitions

The current implementation targets the WorldGuard model of sifive,wgchecker2 checker plus per-hart and per-domain WorldGuard metadata from DT.

The series is organized as follows:
1. add the WorldGuard CSR definitions and hart extension flags needed to detect support for MLWID, MWIDDELEG, and SLWID
2. document the HWISO / WorldGuard device-tree metadata used by the current implementation
3. add a QEMU virt DT overlay that describes domain WID/WID list assignment and checker permission policy for the current test flow
4. add generic-platform WorldGuard runtime support together with wgchecker2 checker parsing and boot-time MMIO programming
5. add generic HWISO SBIUNIT coverage
6. add QEMU virt WorldGuard mechanism-specific SBIUNIT checks for boot-time checker programming and runtime CSR state
7. add a QEMU virt failure-mode SBIUNIT test that intentionally triggers a denied WorldGuard access and verifies the expected trap

Notes:
- The implementation has been verified with QEMU virt that supports wg=on[1].
- This series depends on previous patches ([2] and [3]) for introducing HWISO framework.

[1] https://github.com/cwshu/qemu/tree/riscv-wg-dts
[2] [PATCH 1/2] sbi: add hardware isolation abstraction framework

    https://lore.kernel.org/opensbi/[email protected]/
[3] [PATCH 2/2] sbi: route domain lifecycle transitions through hwiso hooks
    https://lore.kernel.org/opensbi/[email protected]/
Quoted 8 lines

Raymond Mao (7):
hart: add WorldGuard CSR IDs and hart extension flags
docs: document hwiso WorldGuard DT bindings [NOT-FOR-UPSTREAM] platform: virt: add QEMU WorldGuard hwiso overlay
platform: generic: add WorldGuard hwiso support with wgchecker2
test: add generic hwiso SBI unit coverage
platform: virt: add QEMU virt WorldGuard hwiso tests
platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

I will consider this series superseded by "Add RISC-V Worlds ISA support to OpenSBI" posted by Yu-Chein Peter Lin (SiFive).

Regards,
Anup

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#9 lore raw

Hi Anup,

Quoted 53 lines · Anup Patel
Quoted 42 lines · Raymond Mao

From: Raymond Mao <[email protected]>

This series adds WorldGuard implementation for OpenSBI on top of the generic hardware isolation (HWISO) hooks.

The goal is to let OpenSBI:
- program platform WorldGuard checker state at boot
- parse per-domain WorldGuard metadata from the device tree
- reprogram hart WorldGuard runtime state during domain transitions

The current implementation targets the WorldGuard model of sifive,wgchecker2 checker plus per-hart and per-domain WorldGuard metadata from DT.

The series is organized as follows:
1. add the WorldGuard CSR definitions and hart extension flags needed to detect support for MLWID, MWIDDELEG, and SLWID
2. document the HWISO / WorldGuard device-tree metadata used by the current implementation
3. add a QEMU virt DT overlay that describes domain WID/WID list assignment and checker permission policy for the current test flow
4. add generic-platform WorldGuard runtime support together with wgchecker2 checker parsing and boot-time MMIO programming
5. add generic HWISO SBIUNIT coverage
6. add QEMU virt WorldGuard mechanism-specific SBIUNIT checks for boot-time checker programming and runtime CSR state
7. add a QEMU virt failure-mode SBIUNIT test that intentionally triggers a denied WorldGuard access and verifies the expected trap

Notes:
- The implementation has been verified with QEMU virt that supports wg=on[1].
- This series depends on previous patches ([2] and [3]) for introducing HWISO framework.

[1] https://github.com/cwshu/qemu/tree/riscv-wg-dts
[2] [PATCH 1/2] sbi: add hardware isolation abstraction framework

    https://lore.kernel.org/opensbi/[email protected]/
[3] [PATCH 2/2] sbi: route domain lifecycle transitions through hwiso hooks
    https://lore.kernel.org/opensbi/[email protected]/
Quoted 8 lines

Raymond Mao (7):
hart: add WorldGuard CSR IDs and hart extension flags
docs: document hwiso WorldGuard DT bindings [NOT-FOR-UPSTREAM] platform: virt: add QEMU WorldGuard hwiso overlay
platform: generic: add WorldGuard hwiso support with wgchecker2
test: add generic hwiso SBI unit coverage
platform: virt: add QEMU virt WorldGuard hwiso tests
platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

Quoted 3 lines

I will consider this series superseded by "Add RISC-V Worlds ISA support to OpenSBI" posted by Yu-Chein Peter Lin (SiFive).

Not really, the one from Peter is with the ISA and DT-bings but without the WG implementations.
But I will rebase my series on top of his one and send a v2.

Regards,
Raymond

Quoted 2 lines

Regards,
Anup

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#11 lore raw

Hi Peter,

Quoted 9 lines · Peter Lin

Thanks Raymond,

For the WorldGuard checker part, we are still addressing reviewer feedback [1]. Please expect changes that may impact your implementation in OpenSBI.

[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/

Thanks for the update. I will keep tracking the update on that thread.

Regards,
Raymond

Quoted 71 lines · Raymond Mao
Quoted 70 lines

Hi Anup,

Quoted 53 lines · Anup Patel
Quoted 42 lines · Raymond Mao

From: Raymond Mao <[email protected]>

This series adds WorldGuard implementation for OpenSBI on top of the generic hardware isolation (HWISO) hooks.

The goal is to let OpenSBI:
- program platform WorldGuard checker state at boot
- parse per-domain WorldGuard metadata from the device tree
- reprogram hart WorldGuard runtime state during domain transitions

The current implementation targets the WorldGuard model of sifive,wgchecker2 checker plus per-hart and per-domain WorldGuard metadata from DT.

The series is organized as follows:
1. add the WorldGuard CSR definitions and hart extension flags needed to detect support for MLWID, MWIDDELEG, and SLWID
2. document the HWISO / WorldGuard device-tree metadata used by the current implementation
3. add a QEMU virt DT overlay that describes domain WID/WID list assignment and checker permission policy for the current test flow
4. add generic-platform WorldGuard runtime support together with wgchecker2 checker parsing and boot-time MMIO programming
5. add generic HWISO SBIUNIT coverage
6. add QEMU virt WorldGuard mechanism-specific SBIUNIT checks for boot-time checker programming and runtime CSR state
7. add a QEMU virt failure-mode SBIUNIT test that intentionally triggers a denied WorldGuard access and verifies the expected trap

Notes:
- The implementation has been verified with QEMU virt that supports wg=on[1].
- This series depends on previous patches ([2] and [3]) for introducing HWISO framework.

[1] https://github.com/cwshu/qemu/tree/riscv-wg-dts
[2] [PATCH 1/2] sbi: add hardware isolation abstraction framework

    https://lore.kernel.org/opensbi/[email protected]/
[3] [PATCH 2/2] sbi: route domain lifecycle transitions through hwiso hooks
    https://lore.kernel.org/opensbi/[email protected]/
Quoted 8 lines

Raymond Mao (7):
hart: add WorldGuard CSR IDs and hart extension flags
docs: document hwiso WorldGuard DT bindings [NOT-FOR-UPSTREAM] platform: virt: add QEMU WorldGuard hwiso overlay
platform: generic: add WorldGuard hwiso support with wgchecker2
test: add generic hwiso SBI unit coverage
platform: virt: add QEMU virt WorldGuard hwiso tests
platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

Quoted 3 lines

I will consider this series superseded by "Add RISC-V Worlds ISA support to OpenSBI" posted by Yu-Chein Peter Lin (SiFive).

Not really, the one from Peter is with the ISA and DT-bings but without the WG implementations.
But I will rebase my series on top of his one and send a v2.

Regards,
Raymond

Quoted 2 lines

Regards,
Anup

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#12 lore raw
In reply to a message not in the archive

Hi Peter and Anup,

Quoted 9 lines · Peter Lin

Thanks Raymond,

For the WorldGuard checker part, we are still addressing reviewer feedback [1]. Please expect changes that may impact your implementation in OpenSBI.

[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/

I have posted a v2 series "[PATCH v2 0/4] Add WorldGuard support with wgchecker2" [1] based on Anup's series [2] and Peter's DT-binding RFC [3].
All implementations of WG are on top of sbi_hart_protection and sbi_domain_data. Please kindly provide your feedback.

[1] https://lore.kernel.org/opensbi/[email protected]/
[2] https://lore.kernel.org/opensbi/[email protected]/
[3] https://patchwork.kernel.org/project/linux-riscv/list/?series=1113881

Thanks and regards,
Raymond

Quoted 71 lines · Raymond Mao
Quoted 70 lines

Hi Anup,

Quoted 53 lines · Anup Patel
Quoted 42 lines · Raymond Mao

From: Raymond Mao <[email protected]>

This series adds WorldGuard implementation for OpenSBI on top of the generic hardware isolation (HWISO) hooks.

The goal is to let OpenSBI:
- program platform WorldGuard checker state at boot
- parse per-domain WorldGuard metadata from the device tree
- reprogram hart WorldGuard runtime state during domain transitions

The current implementation targets the WorldGuard model of sifive,wgchecker2 checker plus per-hart and per-domain WorldGuard metadata from DT.

The series is organized as follows:
1. add the WorldGuard CSR definitions and hart extension flags needed to detect support for MLWID, MWIDDELEG, and SLWID
2. document the HWISO / WorldGuard device-tree metadata used by the current implementation
3. add a QEMU virt DT overlay that describes domain WID/WID list assignment and checker permission policy for the current test flow
4. add generic-platform WorldGuard runtime support together with wgchecker2 checker parsing and boot-time MMIO programming
5. add generic HWISO SBIUNIT coverage
6. add QEMU virt WorldGuard mechanism-specific SBIUNIT checks for boot-time checker programming and runtime CSR state
7. add a QEMU virt failure-mode SBIUNIT test that intentionally triggers a denied WorldGuard access and verifies the expected trap

Notes:
- The implementation has been verified with QEMU virt that supports wg=on[1].
- This series depends on previous patches ([2] and [3]) for introducing HWISO framework.

[1] https://github.com/cwshu/qemu/tree/riscv-wg-dts
[2] [PATCH 1/2] sbi: add hardware isolation abstraction framework

    https://lore.kernel.org/opensbi/[email protected]/
[3] [PATCH 2/2] sbi: route domain lifecycle transitions through hwiso hooks
    https://lore.kernel.org/opensbi/[email protected]/
Quoted 8 lines

Raymond Mao (7):
hart: add WorldGuard CSR IDs and hart extension flags
docs: document hwiso WorldGuard DT bindings [NOT-FOR-UPSTREAM] platform: virt: add QEMU WorldGuard hwiso overlay
platform: generic: add WorldGuard hwiso support with wgchecker2
test: add generic hwiso SBI unit coverage
platform: virt: add QEMU virt WorldGuard hwiso tests
platform: virt: add WorldGuard HWISO failure-mode SBIUNIT test

Quoted 3 lines

I will consider this series superseded by "Add RISC-V Worlds ISA support to OpenSBI" posted by Yu-Chein Peter Lin (SiFive).

Not really, the one from Peter is with the ISA and DT-bings but without the WG implementations.
But I will rebase my series on top of his one and send a v2.

Regards,
Raymond

Quoted 2 lines

Regards,
Anup

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