Skip to contentSkip to conversation

dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

PATCH Superseded Drew Fustini 3 participants 5 messages May 20

Subsystems (4)
Device tree bindings RISC-V IOMMU RISC-V IOMMU

v2 of 4 Superseded Latest is v4 →

lore
Share & tools
lore

Drew Fustini

author
#0 lore raw

PATCH v2 1/1 dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

From: Nicholas Piggin <[email protected]>

Extend the binding to cover details specific to the Tenstorrent RISC-V IOMMU. In particular, a second register range is added which contains M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register range and are compatible with "riscv,iommu" so the Linux driver does not notice any difference, but the binding will be used by OpenSBI and potentially other M-mode software.

Reviewed-by Joel Stanley <[email protected]>
Acked-by Joerg Roedel <[email protected]>
Signed-off-by Nicholas Piggin <[email protected]>
[fustini: fix dt_binding_check errors]
Signed-off-by Drew Fustini <[email protected]>

---
v2 changes:
- Fix dt_binding_check errors
- Add the Acked-by: from Joerg
- Drop RFC prefix

Link to v1:
https://lore.kernel.org/lkml/[email protected]/

 .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +55 -7
index d4838c3b3741..5aad8cf67840 100644
@@ -32,22 +32,35 @@ properties:
   # should be specified along with 'reg' property providing MMIO location.
   compatible:
     oneOf:
-      - items:
+      - description: Platform (non-PCIe) IOMMU implementations
+        items:
           - enum:
               - qemu,riscv-iommu
           - const: riscv,iommu
-      - items:
+      - description: PCIe IOMMU implementations
+        items:
           - enum:
               - pci1efd,edf1
           - const: riscv,pci-iommu
+      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
+        items:
+          - enum:
+              - tenstorrent,riscv-iommu
+          - const: riscv,iommu
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
     description:
-      For non-PCI devices this represents base address and size of for the
-      IOMMU memory mapped registers interface.
-      For PCI IOMMU hardware implementation this should represent an address
-      of the IOMMU, as defined in the PCI Bus Binding reference.
+      For non-PCI devices the first item represents base address and size of
+      for the IOMMU memory mapped registers interface.
+      For PCI IOMMU hardware implementation the first item should represent
+      an address of the IOMMU, as defined in the PCI Bus Binding reference.
+
+  reg-names:
+    items:
+      - const: base
+      - const: machine
 
   '#iommu-cells':
     const: 1

@@ -75,6 +88,31 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.
+        reg-names:
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
 examples:
   - |+
     /* Example 1 (IOMMU device with wired interrupts) */

@@ -145,3 +183,13 @@ examples:
             };
         };
     };
+
+  - |+
+    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+    iommu5: iommu@d2020000 {
+        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;
+        reg-names = "base", "machine";
+        msi-parent = <&imsics_smode>;
+        #iommu-cells = <1>;
+    };
Signature · 1 line
2.43.0
AI review
#1 lore raw
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Missing Schema Constraints for Hardware Variant --

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing Schema Constraints for Hardware Variant
--

commit 171e0844b229701117691d7ea692a719866e79d9
Author: Nicholas Piggin <[email protected]>

dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

This commit extends the RISC-V IOMMU binding to cover the Tenstorrent variant. It adds a second register range for machine-mode (M-privileged) registers such as PMAs and PMPs.

Quoted 3 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +0 -0

[ ... ]

Quoted 14 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +10 -0
@@ -75,6 +88,31 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 110

Quoted 10 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +10 -0
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.
+        reg-names:
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.

[Severity: Medium]
Should minItems: 2 be explicitly specified for the reg property in this block?

Since the top-level schema allows minItems: 1, a device tree could provide only a single register range and silently pass validation if the tooling does not automatically infer the minimum items from the items list within the conditional block.

Additionally, since the Tenstorrent variant introduces a second distinct register region, should reg-names be added to a required list within this conditional block to guarantee the regions are always properly disambiguated by software?

Quoted 4 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +4 -0
+    else:
+      properties:
+        reg:
+          maxItems: 1
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
#2 lore raw
In reply to Drew Fustini
Quoted 43 lines · Drew Fustini

From: Nicholas Piggin <[email protected]>

Extend the binding to cover details specific to the Tenstorrent RISC-V IOMMU. In particular, a second register range is added which contains M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register range and are compatible with "riscv,iommu" so the Linux driver does not notice any difference, but the binding will be used by OpenSBI and potentially other M-mode software.

Reviewed-by Joel Stanley <[email protected]>
Acked-by Joerg Roedel <[email protected]>
Signed-off-by Nicholas Piggin <[email protected]>
[fustini: fix dt_binding_check errors]
Signed-off-by Drew Fustini <[email protected]>

---
v2 changes:
- Fix dt_binding_check errors
- Add the Acked-by: from Joerg
- Drop RFC prefix

Link to v1:
https://lore.kernel.org/lkml/[email protected]/

 .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +2 -2
index d4838c3b3741..5aad8cf67840 100644
@@ -32,22 +32,35 @@ properties:
   # should be specified along with 'reg' property providing MMIO location.
   compatible:
     oneOf:
-      - items:
+      - description: Platform (non-PCIe) IOMMU implementations
+        items:
           - enum:
               - qemu,riscv-iommu
           - const: riscv,iommu
-      - items:

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml properties: · line 49

Quoted 10 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +7 -0
+      - description: PCIe IOMMU implementations
+        items:
           - enum:
               - pci1efd,edf1
           - const: riscv,pci-iommu
+      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
+        items:
+          - enum:
+              - tenstorrent,riscv-iommu
+          - const: riscv,iommu

You should be able to put this into the enum alongside the qemu compatible, right?

Quoted 30 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +15 -5
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
     description:
-      For non-PCI devices this represents base address and size of for the
-      IOMMU memory mapped registers interface.
-      For PCI IOMMU hardware implementation this should represent an address
-      of the IOMMU, as defined in the PCI Bus Binding reference.
+      For non-PCI devices the first item represents base address and size of
+      for the IOMMU memory mapped registers interface.
+      For PCI IOMMU hardware implementation the first item should represent
+      an address of the IOMMU, as defined in the PCI Bus Binding reference.
+
+  reg-names:
+    items:
+      - const: base
+      - const: machine
 
   '#iommu-cells':
     const: 1

@@ -75,6 +88,31 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 104

Quoted 10 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +9 -0
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
 
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.

Should this also have minItems: 2?

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 110

Quoted 8 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +7 -0
+        reg-names:
 
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.

And this you should replace with minItems: 2 or delete. The reg property is where your description here belongs and all the names do here is re-list what's available outside the condition.

Quoted 9 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +5 -0
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
 examples:

- |+

     /* Example 1 (IOMMU device with wired interrupts) */

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml examples: · line 191

Quoted 9 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +6 -0
@@ -145,3 +183,13 @@ examples:
             };
         };
     };
+
+  - |+
+    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+    iommu5: iommu@d2020000 {
+        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;

This is not the correct format for multiple reg properties. Hint: you're missing ">, <".

pw-bot: changes-requested

Cheers,
Conor.

Quoted 7 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +4 -0
+        reg-names = "base", "machine";
+        msi-parent = <&imsics_smode>;
+        #iommu-cells = <1>;
+    };
Signature · 1 line
2.43.0
author
#3 lore raw

On Wed, May 20, 2026 at 05:17:41PM +0100, Conor Dooley wrote:

Thanks for the review...

Quoted 49 lines · Drew Fustini
Quoted 48 lines

From: Nicholas Piggin <[email protected]>

Extend the binding to cover details specific to the Tenstorrent RISC-V IOMMU. In particular, a second register range is added which contains M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register range and are compatible with "riscv,iommu" so the Linux driver does not notice any difference, but the binding will be used by OpenSBI and potentially other M-mode software.

Reviewed-by Joel Stanley <[email protected]>
Acked-by Joerg Roedel <[email protected]>
Signed-off-by Nicholas Piggin <[email protected]>
[fustini: fix dt_binding_check errors]
Signed-off-by Drew Fustini <[email protected]>

---
v2 changes:
- Fix dt_binding_check errors
- Add the Acked-by: from Joerg
- Drop RFC prefix

Link to v1:
https://lore.kernel.org/lkml/[email protected]/

 .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +4 -2
index d4838c3b3741..5aad8cf67840 100644
@@ -32,22 +32,35 @@ properties:
   # should be specified along with 'reg' property providing MMIO location.
   compatible:
     oneOf:
-      - items:
+      - description: Platform (non-PCIe) IOMMU implementations
+        items:
           - enum:
               - qemu,riscv-iommu
           - const: riscv,iommu
-      - items:
+      - description: PCIe IOMMU implementations
+        items:
           - enum:
               - pci1efd,edf1
           - const: riscv,pci-iommu
Quoted 8 lines

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml properties: · line 49

Quoted 5 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +5 -0
+      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
+        items:
+          - enum:
+              - tenstorrent,riscv-iommu
+          - const: riscv,iommu

You should be able to put this into the enum alongside the qemu compatible, right?

Good point, I'll move tenstorrent,riscv-iommu to the enum with qemu,riscv-iommu.

Quoted 11 lines
Quoted 10 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +10 -0
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
Quoted 5 lines

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 103

Quoted 3 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +3 -0
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.

Should this also have minItems: 2?

I think items: with 2 items implies minItems: 2 but I see your later point about the description and names don't belong in the allOf: block.

Quoted 10 lines

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 110

Quoted 9 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +7 -0
+        reg-names:
 
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.
Quoted 3 lines

And this you should replace with minItems: 2 or delete. The reg property is where your description here belongs and all the names do here is re-list what's available outside the condition.

Ah, so I just have minItems: 2 here and rely on the reg: section to have the descriptions.

Quoted 8 lines

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml examples: · line 191

Quoted 5 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +5 -0
+  - |+
+    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+    iommu5: iommu@d2020000 {
+        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;

This is not the correct format for multiple reg properties. Hint: you're missing ">, <".

Thanks, I'll fix that.

-Drew

#4 lore raw
Quoted 13 lines · Drew Fustini
Quoted 12 lines · Conor Dooley
Quoted 10 lines · Drew Fustini
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +10 -0
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
Quoted 8 lines
Quoted 5 lines

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml required: · line 103

Quoted 3 lines
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +3 -0
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.

Should this also have minItems: 2?

I think items: with 2 items implies minItems: 2 but I see your later point about the description and names don't belong in the allOf: block.

It would usually, but this is a conditional portion of a wider binding that you've modified to look like

| reg:
|  minItems: 1
|  maxItems: 2

outside the conditional section, and since you don't further constrain reg in the conditional section, this minItems: 1 applies.