Skip to contentSkip to conversation

dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

PATCH Superseded Dinh Nguyen 3 participants 6 messages Jun 26

Subsystems (4)
Network drivers Device tree bindings Arm STM32 Arm/socfpga dwmac glue layer

v1 of 2 Superseded Latest is v2 →

lore
Share & tools
lore

Dinh Nguyen

author
#0 lore raw

PATCH 1/2 dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants.

Signed-off-by Dinh Nguyen <[email protected]>
---
 .../bindings/net/altr,socfpga-stmmac.yaml     | 51 +++++++++++++++++--
 1 file changed, 46 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +46 -5
index fc445ad5a1f1..9bae17688992 100644
@@ -62,12 +62,28 @@ properties:
       - const: stmmaceth
       - const: ptp_ref
 
-  interrupts:
-    maxItems: 1
-
   interrupt-names:
-    items:
-      - const: macirq
+    oneOf:
+      - items:
+          - const: macirq
+      - items:
+          - const: macirq
+          - const: tx-queue-0
+          - const: tx-queue-1
+          - const: tx-queue-2
+          - const: tx-queue-3
+          - const: tx-queue-4
+          - const: tx-queue-5
+          - const: tx-queue-6
+          - const: tx-queue-7
+          - const: rx-queue-0
+          - const: rx-queue-1
+          - const: rx-queue-2
+          - const: rx-queue-3
+          - const: rx-queue-4
+          - const: rx-queue-5
+          - const: rx-queue-6
+          - const: rx-queue-7
 
   iommus:
     minItems: 1

@@ -149,10 +165,35 @@ required:
   - clocks
   - clock-names
   - altr,sysmgr-syscon
+  - interrupts
+  - interrupt-names
 
 allOf:
   - $ref: snps,dwmac.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,socfpga-stmmac-agilex5
+    then:
+      properties:
+        interrupts:
+          minItems: 17
+          maxItems: 17
+
+        interrupt-names:
+          minItems: 17
+          maxItems: 17
+
+        dma-coherent: true
+    else:
+      properties:
+        interrupts:
+          minItems: 1
+
+        dma-coherent: false
+
 unevaluatedProperties: false
 
 examples:
Signature · 1 line
2.42.0.411.g813d9a9188
author
#1 lore raw

PATCH 2/2 arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs.

Signed-off-by Dinh Nguyen <[email protected]>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++--
 1 file changed, 68 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +68 -4
index 2096decb5655..f54767d1526e 100644
@@ -702,8 +702,40 @@ gmac1: ethernet@10820000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10820000 0x3500>;
-			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "tx-queue-0",
+					  "tx-queue-1",
+					  "tx-queue-2",
+					  "tx-queue-3",
+					  "tx-queue-4",
+					  "tx-queue-5",
+					  "tx-queue-6",
+					  "tx-queue-7",
+					  "rx-queue-0",
+					  "rx-queue-1",
+					  "rx-queue-2",
+					  "rx-queue-3",
+					  "rx-queue-4",
+					  "rx-queue-5",
+					  "rx-queue-6",
+					  "rx-queue-7";
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 			reset-names = "stmmaceth", "ahb";
 			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,

@@ -816,8 +848,40 @@ gmac2: ethernet@10830000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10830000 0x3500>;
-			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "tx-queue-0",
+					  "tx-queue-1",
+					  "tx-queue-2",
+					  "tx-queue-3",
+					  "tx-queue-4",
+					  "tx-queue-5",
+					  "tx-queue-6",
+					  "tx-queue-7",
+					  "rx-queue-0",
+					  "rx-queue-1",
+					  "rx-queue-2",
+					  "rx-queue-3",
+					  "rx-queue-4",
+					  "rx-queue-5",
+					  "rx-queue-6",
+					  "rx-queue-7";
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 			reset-names = "stmmaceth", "ahb";
 			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
Signature · 1 line
2.42.0.411.g813d9a9188
AI review
#2 lore raw

Re: [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Incomplete DT update: gmac0 is left with an invalid interrupt count that will fail dtbs…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete DT update: gmac0 is left with an invalid interrupt count that will fail dtbs validation. --

commit ce31f4c657e3508e9aef68e6da54a09c1d243026
Author: Dinh Nguyen <[email protected]>

arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs.

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi gmac1: ethernet@10820000 { · line 672

Quoted 8 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
index 02e62d954e949..140e4bf9fb155 100644
@@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
 			compatible = "altr,socfpga-stmmac-agilex5",
 				     "snps,dwxgmac-2.10";
 			reg = <0x10820000 0x3500>;

[Severity: Medium]
Should gmac0 also be updated to include 17 interrupts?

Looking earlier in the same file, gmac0 uses the exact same "altr,socfpga-stmmac-agilex5" compatible string, but this patch leaves it configured with only a single interrupt:

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi:

	gmac0: ethernet@10810000 {
		compatible = "altr,socfpga-stmmac-agilex5",
			     "snps,dwxgmac-2.10";
		reg = <0x10810000 0x3500>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
                ...
	}

Since the device tree binding strictly requires 17 interrupts for this specific compatible string, won't skipping gmac0 result in dtbs_check validation errors and leave its queues without dedicated interrupts at runtime?

Quoted 4 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +2 -2
-			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,

[ ... ]

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#3 lore raw

Re: [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Quoted 12 lines · On 6/25/26 23:31, [email protected] wrote:

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete DT update: gmac0 is left with an invalid interrupt count that will fail dtbs validation. --

commit ce31f4c657e3508e9aef68e6da54a09c1d243026
Author: Dinh Nguyen <[email protected]>

arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs.

Quoted 12 lines

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi gmac1: ethernet@10820000 { · line 672

Quoted 8 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
index 02e62d954e949..140e4bf9fb155 100644
@@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
  			compatible = "altr,socfpga-stmmac-agilex5",
  				     "snps,dwxgmac-2.10";
  			reg = <0x10820000 0x3500>;

[Severity: Medium]
Should gmac0 also be updated to include 17 interrupts?

There was an earlier patch that updatee gmac0 to 17 interrupts:

https://lore.kernel.org/all/20260609131641.28476-1-muhammad.nazim.amirul.nazle.asmade@altera.com/

Dinh

AI review
#4 lore raw
In reply to Dinh Nguyen
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Removing the top-level constraints for `interrupts` and `interrupt-names` without restoring them…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Removing the top-level constraints for interrupts and interrupt-names without restoring them in the else block allows older variants to incorrectly pass schema validation with up to 17 interrupts. --

commit b9bb703e842480b5efde889d362af4d3e53520cb
Author: Dinh Nguyen <[email protected]>

dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5

The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. This commit updates the schema to handle the hardware differences between SoC variants.

Quoted 4 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -0
index fc445ad5a1f1a..9bae17688992c 100644

[ ... ]

Quoted 8 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -3
@@ -62,12 +62,28 @@ properties:
       - const: stmmaceth
       - const: ptp_ref
 
-  interrupts:
-    maxItems: 1
-
   interrupt-names:

[ ... ]

Quoted 1 line
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -0
@@ -149,10 +165,35 @@ required:

[ ... ]

Quoted 13 lines

allOf:
- $ref: snps,dwmac.yaml#

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +10 -0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,socfpga-stmmac-agilex5
+    then:
+      properties:
+        interrupts:
+          minItems: 17
+          maxItems: 17

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 193

Quoted 10 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +10 -0
+
+        interrupt-names:
+          minItems: 17
+          maxItems: 17
+
+        dma-coherent: true
+    else:
+      properties:
+        interrupts:
+          minItems: 1

[Severity: Medium]
Does this missing maxItems constraint allow older variants to incorrectly pass schema validation with up to 17 interrupts?

Since the top-level maxItems: 1 constraint was removed for interrupts, this else block applies to all non-Agilex5 variants but only enforces minItems: 1. Because there are no top-level restrictions stopping it, device trees for older variants (e.g., altr,socfpga-stmmac-a10-s10) could specify multiple interrupts and matching interrupt-names without triggering a schema validation error.

Should maxItems: 1 for interrupts and a matching constraint for interrupt-names be added to this else block to enforce the original strict hardware constraints for prior generations?

Quoted 4 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +3 -0
+
+        dma-coherent: false
+
 unevaluatedProperties: false
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
#5 lore raw
In reply to Dinh Nguyen
Quoted 14 lines · Dinh Nguyen

The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants.

Signed-off-by Dinh Nguyen <[email protected]>
---
 .../bindings/net/altr,socfpga-stmmac.yaml     | 51 +++++++++++++++++--
 1 file changed, 46 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -0
index fc445ad5a1f1..9bae17688992 100644

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml properties: · line 67

Quoted 6 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -3
@@ -62,12 +62,28 @@ properties:
       - const: stmmaceth
       - const: ptp_ref
 
-  interrupts:
-    maxItems: 1
-

The top level should retain the widest constraints, so this should say min 1 max 17.

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml properties: · line 68

Quoted 6 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +3 -2
   interrupt-names:
-    items:
-      - const: macirq
+    oneOf:
+      - items:
+          - const: macirq

This is unneeded, just have one list with everything, since entry 1 is the same for both.

Quoted 22 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +18 -0
+      - items:
+          - const: macirq
+          - const: tx-queue-0
+          - const: tx-queue-1
+          - const: tx-queue-2
+          - const: tx-queue-3
+          - const: tx-queue-4
+          - const: tx-queue-5
+          - const: tx-queue-6
+          - const: tx-queue-7
+          - const: rx-queue-0
+          - const: rx-queue-1
+          - const: rx-queue-2
+          - const: rx-queue-3
+          - const: rx-queue-4
+          - const: rx-queue-5
+          - const: rx-queue-6
+          - const: rx-queue-7
 
   iommus:
     minItems: 1

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 169

Quoted 5 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +2 -0
@@ -149,10 +165,35 @@ required:
   - clocks
   - clock-names
   - altr,sysmgr-syscon
+  - interrupts
+  - interrupt-names

No mention in the commit message of an ABI change.

Quoted 4 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +0 -0
 allOf:
   - $ref: snps,dwmac.yaml#

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 183

Quoted 10 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +10 -0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,socfpga-stmmac-agilex5
+    then:
+      properties:
+        interrupts:
+          minItems: 17
+          maxItems: 17

With the change I suggest for the list, the maxItems here can be removed.

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 187

Quoted 4 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +4 -0
+
+        interrupt-names:
+          minItems: 17
+          maxItems: 17

And here.

Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml required: · line 193

Quoted 6 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +6 -0
+
+        dma-coherent: true
+    else:
+      properties:
+        interrupts:
+          minItems: 1

This should have been maxItems: 1 I think.

pw-bot: changes-requested

Thanks,
Conor.

Quoted 9 lines
Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +3 -0
+
+        dma-coherent: false
+
 unevaluatedProperties: false
 
 examples:
Signature · 1 line
2.42.0.411.g813d9a9188