arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus

The interrupt line of the hym8563 RTC on the Orange Pi 5 Plus is routed to GPIO0_C6, not GPIO0_B0. The vendor device tree uses RK_PC6 for this pin; the mainline board file uses RK_PB0, which does not carry the RTC interrupt on this board.

As a result the alarm interrupt never reaches the SoC, so the RTC alarm cannot be used as a wakeup source on this board.

This was verified on the board by enabling the alarm interrupt (AIE with AF already set, so INT# is asserted) and sampling the EXT_PORT register of all five GPIO banks: GPIO0_C6 is the only pad that follows AIE (high with AIE=0, low with AIE=1, in two off/on cycles), while GPIO0_B0 stays high and its interrupt counter stays at zero.

Switch the interrupt and its pinctrl entry to GPIO0_C6. The board has an external pull-up on this open-drain line, so no internal bias is needed.

With this change the alarm interrupt is delivered while the system is running, and the RTC wakes the SoC out of s2idle.

---
Changes in v2:
- Drop the internal pull-up: the board schematic already has an external pull-up on this line (Ondrej Jirman). Only the pin number changes now.
- Reworded the effect paragraphs to state only what was measured; no functional change.
- Link to v1: https://lore.kernel.org/all/[email protected]/

Notes for reviewers (not part of the commit message):

Measured on an Orange Pi 5 Plus. The input levels of all five GPIO banks were read from their EXT_PORT registers via /dev/mem while toggling the alarm interrupt enable through /sys/class/rtc/rtc0/wakealarm; GPIO0_C6 was the only pad that followed it.

The s2idle wakeup was measured with the v1 form of this patch (same pin, but with the internal pull-up still set): 'PM: Triggering wakeup from IRQ 52'. With bias-disable, as posted here, I re-checked that the alarm interrupt still increments the hym8563 interrupt count at the programmed alarm time, with no spurious interrupts on the level-low line.

Note that on this board the resume itself can still stall later in the USB 2.0 host controllers (a separate issue reported in [1]); with those controllers unbound the full s2idle cycle completes. It does not affect this fix.

[1] https://lore.kernel.org/all/[email protected]/

 arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 145986695720..3f2806284754 100644
@@ -189,7 +189,7 @@ &hdptxphy1 {
 
 &hym8563 {
 	interrupt-parent = <&gpio0>;
-	interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+	interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&hym8563_int>;
 };

@@ -298,7 +298,7 @@ hdmi1_tx_on_h: hdmi1-tx-on-h {
 
 	hym8563 {
 		hym8563_int: hym8563-int {
-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 

base-commit: 1fc5a74b108fc90951890ec513ac81869f5eaff1

2.43.0

Applied, thanks!

[1/1] arm64: dts: rockchip: fix hym8563 interrupt pin on Orange Pi 5 Plus

      commit: dc963c9ec182ec24f0b10f11fe377db00528f7a8

Best regards,

Heiko Stuebner <[email protected]>