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perf/x86/intel: PEBS data-source fixes and OMR updates

PATCH Applied Dapeng Mi 3 participants 37 messages Sep 17 – Sep 22

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Dapeng Mi

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#0 lore raw

cover perf/x86/intel: PEBS data-source fixes and OMR updates

This series fixes several recently identified PEBS data-source issues on both P-cores and E-cores.

On the P-core side, some memory events that can not provide valid PEBS data-source information, like MEM_INST_RETIRED.STLB_MISS_LOADS, are marked as data-source capable, which can lead to incorrect decoding results.

On the E-core side, MEM_UOPS_RETIRED.STORE_LATENCY event isn't set the STORE direction flag, causing store operations to be decoded as loads.

The last three patches add support for precise OMR events and rename the DMR/NVL sysfs attribute from offcore_rsp to offmodule_rsp so the interface matches the underlying OMR events and avoids user confusion.

Patch layout:
- Patches 01-04: Fix E-core memory operation decoding.
- Patches 05-06: Remove events without valid PEBS data-source support from the PEBS constraint tables.
- Patch 07: Fix two incorrect snoop-state decodings for Panther Cove.
- Patch 08: Remove dead code from NVL data-source initialization.
- Patch 09: Update Panther Cove event constraints.
- Patch 10: Add precise OMR event support for DMR/NVL.
- Patches 11-12: Rename the DMR/NVL offcore_rsp sysfs attribute to offmodule_rsp.

Tests:
- Run below commands on ARL and PTL, data source can be correctly parsed for both P-core and E-core.

P-core:

  1. perf record -e cpu_core/MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4/p -d \
     	-c 1000 -a -- sleep 1 && perf script -F data_src 

     output:
     "10268100142 |OP LOAD|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"
  2. perf record -e cpu_core/MEM_TRANS_RETIRED.STORE_SAMPLE/p -d \
    	-c 1000 -a -- sleep 1 && perf script -F data_src

     output:
     "10268100144 |OP STORE|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"
  3. perf record -e cpu_core/MEM_INST_RETIRED.STLB_MISS_LOADS/p -d \
        -c 1000 -a -- sleep 1 && perf script -F data_src

     output:
     "1e05080021 |OP N/A|LVL N/A|SNP N/A|TLB N/A|LCK N/A|BLK  N/A"
  E-core:
  1. perf record -e \ 
      cpu_atom/event=0xd0,umask=0x5,ldlat=0x4,name=MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4/p \
      -d -c 1000 -a -- sleep 1 && perf script -F data_src
     output:
     "10268100142 |OP LOAD|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"
  2. perf record -e \
      cpu_atom/event=0xd0,umask=0x6,name=MEM_UOPS_RETIRED.STORE_LATENCY/p \
      -d -c 1000 -a -- sleep 1 && perf script -F data_src
     output:
     "10668080084 |OP STORE|LVL L3 miss|SNP N/A|TLB L1 or L2 hit|LCK No|BLK  N/A"

- Run below precise OMR events on PTL P-core, records can be captured successfully.

  1. perf record -e cpu_core/MEM_LOAD_L2_MISS_RETIRED.L3_HIT_SAME_CBB/p \
     	-c 1000 -a -- sleep 1
  2. perf record -e cpu_core/MEM_STORE_L2_MISS_RETIRED.L2_OTHER_MODULE.SAME_CBB.HITM.SNP_FWD/p \
        -c 1000 -a -- sleep 1

Dapeng Mi (12):
perf/x86/intel: Fix GRT PEBS load/store direction for latency events perf/x86/intel: Fix CMT PEBS load/store direction for latency events perf/x86/intel: Fix DKT PEBS load/store direction for latency events perf/x86/intel: Update arw_latency_data() mem-op direction handling perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints perf/x86/intel: Remove incorrect PantherCove PEBS data-source
constraints
perf/x86/intel: Correct Panther cove data source snoop states perf/x86/intel: Delete dead NVL PEBS data-source init call perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events perf/x86/intel: Add precise OMR event support for DMR/NVL perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

 arch/x86/events/intel/core.c | 55 ++++++++++++++++++++++++---
 arch/x86/events/intel/ds.c   | 74 +++++++++++++++++-------------------
 arch/x86/events/perf_event.h |  4 --
 3 files changed, 83 insertions(+), 50 deletions(-)

base-commit: 68aca309e49c589f1922f4c5af2370e4df093175

Signature · 1 line
2.34.1
author
#1 lore raw

PATCH 1/12 perf/x86/intel: Fix GRT PEBS load/store direction for latency events

On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction.

This fixes incorrect STORE sample classification.

Fixes 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding for ADL")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)
arch/x86/events/intel/ds.c +13 -3
index 2edff9754eb2..20674871c6c3 100644
@@ -455,6 +455,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
 static u64 __grt_latency_data(struct perf_event *event, u64 status,
 			       u8 dse, bool tlb, bool lock, bool blk)
 {
+	union perf_mem_data_src src;
 	u64 val;
 
 	WARN_ON_ONCE(is_hybrid() &&

@@ -470,7 +471,16 @@ static u64 __grt_latency_data(struct perf_event *event, u64 status,
 	else
 		val |= P(BLK, NA);
 
-	return val;
+	src.val = val;
+
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
+		src.mem_op = P(OP, STORE);
+
+	return src.val;
 }
 
 u64 grt_latency_data(struct perf_event *event, u64 status)

@@ -1288,8 +1298,8 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {
 
 struct event_constraint intel_grt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0x3f),
 	EVENT_CONSTRAINT_END
 };
Signature · 1 line
2.34.1
AI review
#2 lore raw

Re: [PATCH 01/12] perf/x86/intel: Fix GRT PEBS load/store direction for latency events

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 13 lines

On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

Quoted 7 lines

Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction.

This fixes incorrect STORE sample classification.

Fixes 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding for ADL")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
merge bot Applied
#3 lore raw

[tip: perf/urgent] perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     89dc568e8c0be60e05e5fcd0b528c79077d7b84b
Gitweb:        https://git.kernel.org/tip/89dc568e8c0be60e05e5fcd0b528c79077d7b84b
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:23 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:17:00 +02:00

perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification

On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for:

- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction.

This fixes incorrect STORE sample classification.

Fixes 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding for ADL")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.2+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)
arch/x86/events/intel/ds.c +13 -3
index b98029b..fff98f4 100644
@@ -455,6 +455,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
 static u64 __grt_latency_data(struct perf_event *event, u64 status,
 			       u8 dse, bool tlb, bool lock, bool blk)
 {
+	union perf_mem_data_src src;
 	u64 val;
 
 	WARN_ON_ONCE(is_hybrid() &&

@@ -470,7 +471,16 @@ static u64 __grt_latency_data(struct perf_event *event, u64 status,
 	else
 		val |= P(BLK, NA);
 
-	return val;
+	src.val = val;
+
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
+		src.mem_op = P(OP, STORE);
+
+	return src.val;
 }
 
 u64 grt_latency_data(struct perf_event *event, u64 status)

@@ -1291,8 +1301,8 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {
 
 struct event_constraint intel_grt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0x3f),
 	EVENT_CONSTRAINT_END
 };
author
#4 lore raw

PATCH 2/12 perf/x86/intel: Fix CMT PEBS load/store direction for latency events

In reply to Dapeng Mi

Same issue exists on Crestmont, intel_cmt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_cmt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

This fixes incorrect STORE sample classification.

Fixes e99fb45436ea ("perf/x86/intel: Update event constraints and cache_extra_regsfor MTL")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index 20674871c6c3..434adf15d83c 100644
@@ -1305,8 +1305,8 @@ struct event_constraint intel_grt_pebs_event_constraints[] = {
 
 struct event_constraint intel_cmt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff),
 	EVENT_CONSTRAINT_END
 };
Signature · 1 line
2.34.1
AI review
#5 lore raw

Re: [PATCH 02/12] perf/x86/intel: Fix CMT PEBS load/store direction for latency events

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 10 lines

Same issue exists on Crestmont, intel_cmt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Quoted 8 lines

Set explicit LOAD/STORE flags in intel_cmt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

This fixes incorrect STORE sample classification.

Fixes e99fb45436ea ("perf/x86/intel: Update event constraints and cache_extra_regsfor MTL")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
merge bot Applied
#6 lore raw

[tip: perf/urgent] perf/x86/intel: Fix CMT PEBS load/store direction for latency events, to fix sample classification

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     e961d6db42d1f1b66c81438969a648f08573bd9c
Gitweb:        https://git.kernel.org/tip/e961d6db42d1f1b66c81438969a648f08573bd9c
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:24 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:17:15 +02:00

perf/x86/intel: Fix CMT PEBS load/store direction for latency events, to fix sample classification

The same bug exists on Crestmont as on Gracemont:
intel_cmt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_cmt_pebs_event_constraints[] for:

- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

This fixes incorrect STORE sample classification.

Fixes e99fb45436ea ("perf/x86/intel: Update event constraints and cache_extra_regsfor MTL")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.2+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index fff98f4..fa7e026 100644
@@ -1308,8 +1308,8 @@ struct event_constraint intel_grt_pebs_event_constraints[] = {
 
 struct event_constraint intel_cmt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff),
 	EVENT_CONSTRAINT_END
 };
author
#7 lore raw

PATCH 3/12 perf/x86/intel: Fix DKT PEBS load/store direction for latency events

In reply to Dapeng Mi

Same issue exists on Darkmont, intel_dkt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_dkt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

This fixes incorrect STORE sample classification. Additionally remove INTEL_HYBRID_LAT_CONSTRAINT() since no one uses it anymore.

Fixes 65fd435095bb ("perf/x86/intel: Update event constraints for PTL")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c   | 4 ++--
 arch/x86/events/perf_event.h | 4 ----
 2 files changed, 2 insertions(+), 6 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index 434adf15d83c..95b3ed3097ab 100644
@@ -1312,8 +1312,8 @@ struct event_constraint intel_cmt_pebs_event_constraints[] = {
 
 struct event_constraint intel_dkt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0xff),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff),
 	EVENT_CONSTRAINT_END
 };
arch/x86/events/perf_event.h +0 -4
index c9c52f3ee4fc..5787053dd40a 100644
@@ -710,10 +710,6 @@ struct cpu_hw_events {
 	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 
-#define INTEL_HYBRID_LAT_CONSTRAINT(c, n)	\
-	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
-			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID)
-
 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n)	\
 	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW)
Signature · 1 line
2.34.1
AI review
#8 lore raw

Re: [PATCH 03/12] perf/x86/intel: Fix DKT PEBS load/store direction for latency events

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 14 lines

Same issue exists on Darkmont, intel_dkt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_dkt_pebs_event_constraints[] for:
- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

Quoted 5 lines

This fixes incorrect STORE sample classification. Additionally remove INTEL_HYBRID_LAT_CONSTRAINT() since no one uses it anymore.

Fixes 65fd435095bb ("perf/x86/intel: Update event constraints for PTL")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
merge bot Applied
#9 lore raw

[tip: perf/urgent] perf/x86/intel: Fix DKT PEBS load/store direction for latency events, to fix sample classification

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     8302c5f475fa5a4ed36a7d32c7b965023d5d7066
Gitweb:        https://git.kernel.org/tip/8302c5f475fa5a4ed36a7d32c7b965023d5d7066
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:25 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:17:59 +02:00

perf/x86/intel: Fix DKT PEBS load/store direction for latency events, to fix sample classification

Same bug exists on Darkmont as on Gracemont:
intel_dkt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events.

The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs.

Set explicit LOAD/STORE flags in intel_dkt_pebs_event_constraints[] for:

- MEM_UOPS_RETIRED.LOAD_LATENCY
- MEM_UOPS_RETIRED.STORE_LATENCY

This fixes incorrect STORE sample classification. Additionally remove INTEL_HYBRID_LAT_CONSTRAINT() since no one uses it anymore.

Fixes 65fd435095bb ("perf/x86/intel: Update event constraints for PTL")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.2+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c   | 4 ++--
 arch/x86/events/perf_event.h | 4 ----
 2 files changed, 2 insertions(+), 6 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index fa7e026..ea5b331 100644
@@ -1315,8 +1315,8 @@ struct event_constraint intel_cmt_pebs_event_constraints[] = {
 
 struct event_constraint intel_dkt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+	INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0xff),
+	INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff),
 	EVENT_CONSTRAINT_END
 };
arch/x86/events/perf_event.h +0 -4
index 4680cba..fab9da7 100644
@@ -517,10 +517,6 @@ struct cpu_hw_events {
 	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 
-#define INTEL_HYBRID_LAT_CONSTRAINT(c, n)	\
-	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
-			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID)
-
 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n)	\
 	__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW)
author
#10 lore raw

PATCH 4/12 perf/x86/intel: Update arw_latency_data() mem-op direction handling

In reply to Dapeng Mi

Align arw_latency_data() with other *_latency_data() helpers by explicitly decoding LOAD/STORE event flags when setting the sampled memory operation direction.

This keeps the latency data path behavior consistent across platforms and avoids relying on implicit direction inference.

Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
arch/x86/events/intel/ds.c +5 -1
index 95b3ed3097ab..a189a68f5e85 100644
@@ -538,7 +538,11 @@ static u64 arw_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;
Signature · 1 line
2.34.1
AI review
#11 lore raw

Re: [PATCH 04/12] perf/x86/intel: Update arw_latency_data() mem-op direction handling

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 8 lines

Align arw_latency_data() with other *_latency_data() helpers by explicitly decoding LOAD/STORE event flags when setting the sampled memory operation direction.

This keeps the latency data path behavior consistent across platforms and avoids relying on implicit direction inference.

Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=4
merge bot Applied
#12 lore raw

[tip: perf/urgent] perf/x86/intel: Update arw_latency_data() mem-op direction handling

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     335b0642812ee0f2b7798b634ce507b8b7c9fe0c
Gitweb:        https://git.kernel.org/tip/335b0642812ee0f2b7798b634ce507b8b7c9fe0c
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:26 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:19:35 +02:00

perf/x86/intel: Update arw_latency_data() mem-op direction handling

Align arw_latency_data() with other *_latency_data() helpers by explicitly decoding LOAD/STORE event flags when setting the sampled memory operation direction.

This keeps the latency data path behavior consistent across platforms and avoids relying on implicit direction inference.

Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
arch/x86/events/intel/ds.c +5 -1
index ea5b331..c0004b0 100644
@@ -538,7 +538,11 @@ static u64 arw_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;
author
#13 lore raw

PATCH 5/12 perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints

In reply to Dapeng Mi

On Lion Cove, PEBS data source is valid only for the events:
- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_lnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Lion Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Also update lnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 22 +++++-----------------
 1 file changed, 5 insertions(+), 17 deletions(-)
arch/x86/events/intel/ds.c +5 -17
index a189a68f5e85..a4581f292966 100644
@@ -577,7 +577,11 @@ static u64 lnc_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;

@@ -1507,24 +1511,8 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1),		/* OCR.* events */
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1),		/* OCR.* events */
 
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1),		/* TOPDOWN.BAD_SPEC_SLOTS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1),		/* TOPDOWN.BR_MISPREDICT_SLOTS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8),		/* TOPDOWN.MEMORY_BOUND_SLOTS */
-
 	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
 	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),	/* MEM_INST_RETIRED.LOCK_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff),		/* MEM_INST_RETIRED.ANY */
-
-	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
-
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
 
 	/*
 	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
Signature · 1 line
2.34.1
AI review
#14 lore raw

Re: [PATCH 05/12] perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 19 lines

On Lion Cove, PEBS data source is valid only for the events:
- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_lnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Lion Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Quoted 6 lines

Also update lnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5
merge bot Applied
#15 lore raw

[tip: perf/urgent] perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     7c944595cc43a664019edc22505b6d6f6039be5e
Gitweb:        https://git.kernel.org/tip/7c944595cc43a664019edc22505b6d6f6039be5e
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:27 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:26:27 +02:00

perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints

On Lion Cove, PEBS data source is valid only for these events:

- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_lnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Lion Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Also update lnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 22 +++++-----------------
 1 file changed, 5 insertions(+), 17 deletions(-)
arch/x86/events/intel/ds.c +5 -17
index c0004b0..cbcc0b3 100644
@@ -577,7 +577,11 @@ static u64 lnc_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;

@@ -1510,24 +1514,8 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1),		/* OCR.* events */
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1),		/* OCR.* events */
 
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1),		/* TOPDOWN.BAD_SPEC_SLOTS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1),		/* TOPDOWN.BR_MISPREDICT_SLOTS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8),		/* TOPDOWN.MEMORY_BOUND_SLOTS */
-
 	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
 	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),	/* MEM_INST_RETIRED.LOCK_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff),		/* MEM_INST_RETIRED.ANY */
-
-	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
-
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
 
 	/*
 	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
author
#16 lore raw

PATCH 6/12 perf/x86/intel: Remove incorrect PantherCove PEBS data-source constraints

In reply to Dapeng Mi

Same issue exists on Panther Cove, PEBS data source is valid only for the events:
- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_pnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Pather Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Also update pnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)
arch/x86/events/intel/ds.c +5 -13
index a4581f292966..7a67fb675b43 100644
@@ -639,7 +639,11 @@ u64 pnc_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;

@@ -1525,18 +1529,6 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
 struct event_constraint intel_pnc_pebs_event_constraints[] = {
 	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
 	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),	/* MEM_INST_RETIRED.LOCK_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */
-
-	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
-
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf),
 
 	/*
 	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
Signature · 1 line
2.34.1
AI review
#17 lore raw

Re: [PATCH 06/12] perf/x86/intel: Remove incorrect PantherCove PEBS data-source constraints

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 20 lines

Same issue exists on Panther Cove, PEBS data source is valid only for the events:
- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_pnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Pather Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Quoted 6 lines

Also update pnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6
merge bot Applied
#18 lore raw

[tip: perf/urgent] perf/x86/intel: Remove incorrect Panther Cove PEBS data-source constraints

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     9f93d33ad65af9853974c1ec4ba1f937e8ba1376
Gitweb:        https://git.kernel.org/tip/9f93d33ad65af9853974c1ec4ba1f937e8ba1376
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:28 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:31:40 +02:00

perf/x86/intel: Remove incorrect Panther Cove PEBS data-source constraints

Same issue exists on Panther Cove, PEBS data source is valid only for these events:

- MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd)
- MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd)

The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_pnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable.

As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users.

Remove those non-data-source memory events from the Pather Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints.

Also update pnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.0+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)
arch/x86/events/intel/ds.c +5 -13
index cbcc0b3..72179bc 100644
@@ -639,7 +639,11 @@ u64 pnc_latency_data(struct perf_event *event, u64 status)
 		val |= P(BLK, NA);
 
 	src.val = val;
-	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW))
+		src.mem_op = P(OP, LOAD);
+	if (event->hw.flags &
+	    (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW))
 		src.mem_op = P(OP, STORE);
 
 	return src.val;

@@ -1528,18 +1532,6 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
 struct event_constraint intel_pnc_pebs_event_constraints[] = {
 	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
 	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),	/* MEM_INST_RETIRED.LOCK_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */
-	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */
-
-	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
-
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
-	INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf),
 
 	/*
 	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
author
#19 lore raw

PATCH 7/12 perf/x86/intel: Correct Panther cove data source snoop states

In reply to Dapeng Mi

For Panthercove, the snoop states for the data source encodings "Prefetch Promotion" and "Cross Core Prefetch Promotion" should be SNOOP_NONE instead of SNOOP_MISS.

Correct the incorrect snooping states for Panther cove.

Fixes d2bdcde9626c ("perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/ds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index 7a67fb675b43..24ec9bc63d2d 100644
@@ -277,8 +277,8 @@ static u64 pnc_pebs_l2_hit_data_source[PNC_PEBS_DATA_SOURCE_MAX] = {
 	0,							/* 0x06: Reserved */
 	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, HIT),	/* 0x07: L2 Hit Snoop HIT */
 	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, HITM),	/* 0x08: L2 Hit Snoop Hit Modified */
-	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, MISS),	/* 0x09: Prefetch Promotion */
-	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, MISS),	/* 0x0a: Cross Core Prefetch Promotion */
+	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),	/* 0x09: Prefetch Promotion */
+	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),	/* 0x0a: Cross Core Prefetch Promotion */
 	0,							/* 0x0b: Reserved */
 	0,							/* 0x0c: Reserved */
 	0,							/* 0x0d: Reserved */
Signature · 1 line
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AI review
#20 lore raw

Re: [PATCH 07/12] perf/x86/intel: Correct Panther cove data source snoop states

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 8 lines

For Panthercove, the snoop states for the data source encodings "Prefetch Promotion" and "Cross Core Prefetch Promotion" should be SNOOP_NONE instead of SNOOP_MISS.

Correct the incorrect snooping states for Panther cove.

Fixes d2bdcde9626c ("perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
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merge bot Applied
#21 lore raw

[tip: perf/urgent] perf/x86/intel: Fix Panther Cove PEBS data-source snoop states

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     0ac5d6ca2c3b7d047963b67dccef17902dc6c017
Gitweb:        https://git.kernel.org/tip/0ac5d6ca2c3b7d047963b67dccef17902dc6c017
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:29 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:33:06 +02:00

perf/x86/intel: Fix Panther Cove PEBS data-source snoop states

For Panther Cove, the snoop states for the data source encodings "Prefetch Promotion" and "Cross Core Prefetch Promotion" should be SNOOP_NONE instead of SNOOP_MISS.

Fix the incorrect snooping states for Panther Cove.

Fixes d2bdcde9626c ("perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.0+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/ds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/ds.c +2 -2
index 72179bc..d0329a7 100644
@@ -277,8 +277,8 @@ static u64 pnc_pebs_l2_hit_data_source[PNC_PEBS_DATA_SOURCE_MAX] = {
 	0,							/* 0x06: Reserved */
 	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, HIT),	/* 0x07: L2 Hit Snoop HIT */
 	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, HITM),	/* 0x08: L2 Hit Snoop Hit Modified */
-	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, MISS),	/* 0x09: Prefetch Promotion */
-	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, MISS),	/* 0x0a: Cross Core Prefetch Promotion */
+	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),	/* 0x09: Prefetch Promotion */
+	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),	/* 0x0a: Cross Core Prefetch Promotion */
 	0,							/* 0x0b: Reserved */
 	0,							/* 0x0c: Reserved */
 	0,							/* 0x0d: Reserved */
author
#22 lore raw

PATCH 8/12 perf/x86/intel: Delete dead NVL PEBS data-source init call

In reply to Dapeng Mi

Nova Lake now uses the OMR data-source table for PEBS data-source decoding and no longer depends on the legacy static pebs_data_source[] mapping.

Remove the dead intel_pmu_pebs_data_source_lnl() initialization call for NVL.

Fixes c847a208f43b ("perf/x86/intel: Add core PMU support for Novalake")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/core.c | 2 --
 1 file changed, 2 deletions(-)
arch/x86/events/intel/core.c +0 -2
index 4bde7362d7b2..e6efd2a2ada6 100644
@@ -8843,8 +8843,6 @@ __init int intel_pmu_init(void)
 		/* Initialize Atom core specific PerfMon capabilities.*/
 		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
 		intel_pmu_init_arw(&pmu->pmu);
-
-		intel_pmu_pebs_data_source_lnl();
 		break;
 
 	default:
Signature · 1 line
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AI review
#23 lore raw

Re: [PATCH 08/12] perf/x86/intel: Delete dead NVL PEBS data-source init call

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 9 lines

Nova Lake now uses the OMR data-source table for PEBS data-source decoding and no longer depends on the legacy static pebs_data_source[] mapping.

Remove the dead intel_pmu_pebs_data_source_lnl() initialization call for NVL.

Fixes c847a208f43b ("perf/x86/intel: Add core PMU support for Novalake")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=8
merge bot Applied
#24 lore raw

[tip: perf/urgent] perf/x86/intel: Delete dead NVL PEBS data-source initcall

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     858b37ca19d3f695f7fa94cd14be5a856fd8e7d7
Gitweb:        https://git.kernel.org/tip/858b37ca19d3f695f7fa94cd14be5a856fd8e7d7
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:30 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:33:49 +02:00

perf/x86/intel: Delete dead NVL PEBS data-source initcall

Nova Lake now uses the OMR data-source table for PEBS data-source decoding and no longer depends on the legacy static pebs_data_source[] mapping.

Remove the dead intel_pmu_pebs_data_source_lnl() initialization call for NVL.

Fixes c847a208f43b ("perf/x86/intel: Add core PMU support for Novalake")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/core.c | 2 --
 1 file changed, 2 deletions(-)
arch/x86/events/intel/core.c +0 -2
index 757d408..a7dbbed 100644
@@ -8824,8 +8824,6 @@ __init int intel_pmu_init(void)
 		/* Initialize Atom core specific PerfMon capabilities.*/
 		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
 		intel_pmu_init_arw(&pmu->pmu);
-
-		intel_pmu_pebs_data_source_lnl();
 		break;
 
 	default:
author
#25 lore raw

PATCH 9/12 perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events

In reply to Dapeng Mi

Per the latest PantherCove event definitions, the following events are only supported on PMCs 0-3:
- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)

Add explicit event constraints for these two events so scheduling does not place them on unsupported counters.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/core.c | 2 ++
 1 file changed, 2 insertions(+)
arch/x86/events/intel/core.c +2 -0
index e6efd2a2ada6..9462862bf72a 100644
@@ -506,6 +506,8 @@ static struct event_constraint intel_pnc_event_constraints[] = {
 	INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 
 	INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
+	INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf),
+	INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
Signature · 1 line
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AI review
#26 lore raw

Re: [PATCH 09/12] perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 10 lines

Per the latest PantherCove event definitions, the following events are only supported on PMCs 0-3:
- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)

Add explicit event constraints for these two events so scheduling does not place them on unsupported counters.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=9
merge bot Applied
#27 lore raw

[tip: perf/urgent] perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     04a7ef3b7aa3af34202285043e3423a2e3983595
Gitweb:        https://git.kernel.org/tip/04a7ef3b7aa3af34202285043e3423a2e3983595
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:31 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:35:40 +02:00

perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3

Per the latest Panther Cove event definitions, the following events are only supported on PMCs 0-3:

- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)

Add explicit event constraints for these two events so scheduling does not place them on unsupported counters.

Fixes d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Cc <[email protected]> # v7.0+
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/core.c | 2 ++
 1 file changed, 2 insertions(+)
arch/x86/events/intel/core.c +2 -0
index a7dbbed..ecf6d63 100644
@@ -506,6 +506,8 @@ static struct event_constraint intel_pnc_event_constraints[] = {
 	INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 
 	INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
+	INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf),
+	INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
 	INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
author
#28 lore raw

PATCH 10/12 perf/x86/intel: Add precise OMR event support for DMR/NVL

In reply to Dapeng Mi

The latest perfmon event database introduces below precise OMR event support for DMR/NVL:
- MEM_LOAD_L2_MISS_RETIRED.* (event 0xd6)
- MEM_STORE_L2_MISS_RETIRED.* (event 0x4f)

These events use the same OMR MSRs as the existing OMR events, but they are not listed in intel_pnc_extra_regs[]. As a result, perf cannot assign the required OMR extra registers when scheduling them.

Add the new precise OMR events to intel_pnc_extra_regs[] so they can be scheduled with the correct OMR MSRs. MEM_LOAD_L2_MISS_RETIRED.* remains limited to GP counters 0-3, while MEM_STORE_L2_MISS_RETIRED.* is available on all GP counters.

Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/core.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/x86/events/intel/core.c +8 -0
index 9462862bf72a..276a54416d5c 100644
@@ -522,6 +522,14 @@ static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
 	INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
 	INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
+	INTEL_UEVENT_EXTRA_REG(0x014f, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
+	INTEL_UEVENT_EXTRA_REG(0x024f, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
+	INTEL_UEVENT_EXTRA_REG(0x044f, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
+	INTEL_UEVENT_EXTRA_REG(0x084f, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
+	INTEL_UEVENT_EXTRA_REG(0x01d6, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
+	INTEL_UEVENT_EXTRA_REG(0x02d6, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
+	INTEL_UEVENT_EXTRA_REG(0x04d6, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
+	INTEL_UEVENT_EXTRA_REG(0x08d6, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
 	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
Signature · 1 line
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AI review
#29 lore raw

Re: [PATCH 10/12] perf/x86/intel: Add precise OMR event support for DMR/NVL

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 9 lines

The latest perfmon event database introduces below precise OMR event support for DMR/NVL:
- MEM_LOAD_L2_MISS_RETIRED.* (event 0xd6)
- MEM_STORE_L2_MISS_RETIRED.* (event 0x4f)

These events use the same OMR MSRs as the existing OMR events, but they are not listed in intel_pnc_extra_regs[]. As a result, perf cannot assign the required OMR extra registers when scheduling them.

Quoted 6 lines

Add the new precise OMR events to intel_pnc_extra_regs[] so they can be scheduled with the correct OMR MSRs. MEM_LOAD_L2_MISS_RETIRED.* remains limited to GP counters 0-3, while MEM_STORE_L2_MISS_RETIRED.* is available on all GP counters.

Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=10
merge bot Applied
#30 lore raw

[tip: perf/urgent] perf/x86/intel: Fix precise OMR event scheduling for DMR/NVL

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     ff1621adfdd7cfb73f2ccdd3856cd3462ac98ac5
Gitweb:        https://git.kernel.org/tip/ff1621adfdd7cfb73f2ccdd3856cd3462ac98ac5
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:32 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:37:00 +02:00

perf/x86/intel: Fix precise OMR event scheduling for DMR/NVL

The latest perfmon event database introduces below precise OMR event support for DMR/NVL:

- MEM_LOAD_L2_MISS_RETIRED.* (event 0xd6)
- MEM_STORE_L2_MISS_RETIRED.* (event 0x4f)

These events use the same OMR MSRs as the existing OMR events, but they are not listed in intel_pnc_extra_regs[]. As a result, perf cannot assign the required OMR extra registers when scheduling them.

Add the new precise OMR events to intel_pnc_extra_regs[] so they can be scheduled with the correct OMR MSRs. MEM_LOAD_L2_MISS_RETIRED.* remains limited to GP counters 0-3, while MEM_STORE_L2_MISS_RETIRED.* is available on all GP counters.

Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/core.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/x86/events/intel/core.c +8 -0
index ecf6d63..2271560 100644
@@ -522,6 +522,14 @@ static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
 	INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
 	INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
+	INTEL_UEVENT_EXTRA_REG(0x014f, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
+	INTEL_UEVENT_EXTRA_REG(0x024f, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
+	INTEL_UEVENT_EXTRA_REG(0x044f, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
+	INTEL_UEVENT_EXTRA_REG(0x084f, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
+	INTEL_UEVENT_EXTRA_REG(0x01d6, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
+	INTEL_UEVENT_EXTRA_REG(0x02d6, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
+	INTEL_UEVENT_EXTRA_REG(0x04d6, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
+	INTEL_UEVENT_EXTRA_REG(0x08d6, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
 	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
author
#31 lore raw

PATCH 11/12 perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp

In reply to Dapeng Mi

DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion.

Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/core.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)
arch/x86/events/intel/core.c +20 -3
index 276a54416d5c..963d391af2ee 100644
@@ -6620,6 +6620,8 @@ static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
 
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
+PMU_FORMAT_ATTR(offmodule_rsp, "config1:0-63");
+
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 
 PMU_FORMAT_ATTR(frontend, "config1:0-23");

@@ -6668,6 +6670,20 @@ static struct attribute *skl_format_attr[] = {
 	NULL,
 };
 
+static struct attribute *pnc_format_attr_rtm[] = {
+	&format_attr_in_tx.attr,
+	&format_attr_in_tx_cp.attr,
+	&format_attr_offmodule_rsp.attr,
+	&format_attr_ldlat.attr,
+	NULL
+};
+
+static struct attribute *pnc_format_attr[] = {
+	&format_attr_offmodule_rsp.attr,
+	&format_attr_ldlat.attr,
+	NULL
+};
+
 static __initconst const struct x86_pmu core_pmu = {
 	.name			= "core",
 	.handle_irq		= x86_pmu_handle_irq,

@@ -8608,6 +8624,8 @@ __init int intel_pmu_init(void)
 	case INTEL_DIAMONDRAPIDS_X:
 		intel_pmu_init_pnc(NULL);
 		x86_pmu.pebs_latency_data = pnc_latency_data;
+		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
+			     pnc_format_attr_rtm : pnc_format_attr;
 
 		pr_cont("Panthercove events, ");
 		name = "panthercove";

@@ -8616,13 +8634,12 @@ __init int intel_pmu_init(void)
 	glc_common:
 		intel_pmu_init_glc(NULL);
 		intel_pmu_pebs_data_source_skl(true);
-
+		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
+			hsw_format_attr : nhm_format_attr;
 	glc_base:
 		x86_pmu.pebs_ept = 1;
 		x86_pmu.hw_config = hsw_hw_config;
 		x86_pmu.get_event_constraints = glc_get_event_constraints;
-		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
-			hsw_format_attr : nhm_format_attr;
 		extra_skl_attr = skl_format_attr;
 		mem_attr = glc_events_attrs;
 		td_attr = glc_td_events_attrs;
Signature · 1 line
2.34.1
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#32 lore raw

Re: [PATCH 11/12] perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 8 lines

DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion.

Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=11
merge bot Applied
#33 lore raw

[tip: perf/urgent] perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     0102c8c7fdfc4bd700971daff2b94470f4eafae4
Gitweb:        https://git.kernel.org/tip/0102c8c7fdfc4bd700971daff2b94470f4eafae4
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:33 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:37:46 +02:00

perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp

DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user & tooling confusion.

Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/core.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)
arch/x86/events/intel/core.c +20 -3
index 2271560..3843dbe 100644
@@ -6601,6 +6601,8 @@ static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
 
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
+PMU_FORMAT_ATTR(offmodule_rsp, "config1:0-63");
+
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 
 PMU_FORMAT_ATTR(frontend, "config1:0-23");

@@ -6649,6 +6651,20 @@ static struct attribute *skl_format_attr[] = {
 	NULL,
 };
 
+static struct attribute *pnc_format_attr_rtm[] = {
+	&format_attr_in_tx.attr,
+	&format_attr_in_tx_cp.attr,
+	&format_attr_offmodule_rsp.attr,
+	&format_attr_ldlat.attr,
+	NULL
+};
+
+static struct attribute *pnc_format_attr[] = {
+	&format_attr_offmodule_rsp.attr,
+	&format_attr_ldlat.attr,
+	NULL
+};
+
 static __initconst const struct x86_pmu core_pmu = {
 	.name			= "core",
 	.handle_irq		= x86_pmu_handle_irq,

@@ -8589,6 +8605,8 @@ __init int intel_pmu_init(void)
 	case INTEL_DIAMONDRAPIDS_X:
 		intel_pmu_init_pnc(NULL);
 		x86_pmu.pebs_latency_data = pnc_latency_data;
+		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
+			     pnc_format_attr_rtm : pnc_format_attr;
 
 		pr_cont("Panthercove events, ");
 		name = "panthercove";

@@ -8597,13 +8615,12 @@ __init int intel_pmu_init(void)
 	glc_common:
 		intel_pmu_init_glc(NULL);
 		intel_pmu_pebs_data_source_skl(true);
-
+		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
+			hsw_format_attr : nhm_format_attr;
 	glc_base:
 		x86_pmu.pebs_ept = 1;
 		x86_pmu.hw_config = hsw_hw_config;
 		x86_pmu.get_event_constraints = glc_get_event_constraints;
-		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
-			hsw_format_attr : nhm_format_attr;
 		extra_skl_attr = skl_format_attr;
 		mem_attr = glc_events_attrs;
 		td_attr = glc_td_events_attrs;
author
#34 lore raw

PATCH 12/12 perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

In reply to Dapeng Mi

NVL introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the NVL PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion.

Signed-off-by Dapeng Mi <[email protected]>
---
 arch/x86/events/intel/core.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)
arch/x86/events/intel/core.c +19 -1
index 963d391af2ee..7b7e1e1c90af 100644
@@ -7549,6 +7549,7 @@ static struct attribute *adl_hybrid_tsx_attrs[] = {
 FORMAT_ATTR_HYBRID(in_tx,       hybrid_big);
 FORMAT_ATTR_HYBRID(in_tx_cp,    hybrid_big);
 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
+FORMAT_ATTR_HYBRID(offmodule_rsp, hybrid_big_small_tiny);
 FORMAT_ATTR_HYBRID(ldlat,       hybrid_big_small_tiny);
 FORMAT_ATTR_HYBRID(frontend,    hybrid_big);
 

@@ -7587,6 +7588,23 @@ static struct attribute *mtl_hybrid_extra_attr[] = {
 	NULL
 };
 
+static struct attribute *nvl_hybrid_extra_attr_rtm[] = {
+	ADL_HYBRID_RTM_FORMAT_ATTR,
+	FORMAT_HYBRID_PTR(offmodule_rsp),
+	FORMAT_HYBRID_PTR(ldlat),
+	FORMAT_HYBRID_PTR(frontend),
+	FORMAT_HYBRID_PTR(snoop_rsp),
+	NULL
+};
+
+static struct attribute *nvl_hybrid_extra_attr[] = {
+	FORMAT_HYBRID_PTR(offmodule_rsp),
+	FORMAT_HYBRID_PTR(ldlat),
+	FORMAT_HYBRID_PTR(frontend),
+	FORMAT_HYBRID_PTR(snoop_rsp),
+	NULL
+};
+
 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
 {
 	struct device *dev = kobj_to_dev(kobj);

@@ -8861,7 +8879,7 @@ __init int intel_pmu_init(void)
 		mem_attr = mtl_hybrid_mem_attrs;
 		tsx_attr = adl_hybrid_tsx_attrs;
 		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
-			mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
+			nvl_hybrid_extra_attr_rtm : nvl_hybrid_extra_attr;
 
 		/* Initialize big core specific PerfMon capabilities.*/
 		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
Signature · 1 line
2.34.1
AI review
#35 lore raw

Re: [PATCH 12/12] perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

Sashiko has reviewed this patch and found no issues. It looks great!
Quoted 8 lines

NVL introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the NVL PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion.

Signed-off-by Dapeng Mi <[email protected]>

Sashiko has reviewed this patch and found no issues. It looks great!

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=12
merge bot Applied
#36 lore raw

[tip: perf/urgent] perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

In reply to Dapeng Mi
The following commit has been merged into the perf/urgent branch of tip:

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     d4d9ccbad527af115b8e83a7a2b74785c0e8dfea
Gitweb:        https://git.kernel.org/tip/d4d9ccbad527af115b8e83a7a2b74785c0e8dfea
Author:        Dapeng Mi <[email protected]>
AuthorDate:    Thu, 17 Sep 2026 09:52:34 +08:00
Committer:     Ingo Molnar <[email protected]>
CommitterDate: Tue, 22 Sep 2026 11:38:17 +02:00

perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

NVL introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the NVL PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user & tooling confusion.

Signed-off-by Dapeng Mi <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://patch.msgid.link/[email protected] open here
---
 arch/x86/events/intel/core.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)
arch/x86/events/intel/core.c +19 -1
index 3843dbe..3ef8088 100644
@@ -7530,6 +7530,7 @@ static struct attribute *adl_hybrid_tsx_attrs[] = {
 FORMAT_ATTR_HYBRID(in_tx,       hybrid_big);
 FORMAT_ATTR_HYBRID(in_tx_cp,    hybrid_big);
 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
+FORMAT_ATTR_HYBRID(offmodule_rsp, hybrid_big_small_tiny);
 FORMAT_ATTR_HYBRID(ldlat,       hybrid_big_small_tiny);
 FORMAT_ATTR_HYBRID(frontend,    hybrid_big);
 

@@ -7568,6 +7569,23 @@ static struct attribute *mtl_hybrid_extra_attr[] = {
 	NULL
 };
 
+static struct attribute *nvl_hybrid_extra_attr_rtm[] = {
+	ADL_HYBRID_RTM_FORMAT_ATTR,
+	FORMAT_HYBRID_PTR(offmodule_rsp),
+	FORMAT_HYBRID_PTR(ldlat),
+	FORMAT_HYBRID_PTR(frontend),
+	FORMAT_HYBRID_PTR(snoop_rsp),
+	NULL
+};
+
+static struct attribute *nvl_hybrid_extra_attr[] = {
+	FORMAT_HYBRID_PTR(offmodule_rsp),
+	FORMAT_HYBRID_PTR(ldlat),
+	FORMAT_HYBRID_PTR(frontend),
+	FORMAT_HYBRID_PTR(snoop_rsp),
+	NULL
+};
+
 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
 {
 	struct device *dev = kobj_to_dev(kobj);

@@ -8842,7 +8860,7 @@ __init int intel_pmu_init(void)
 		mem_attr = mtl_hybrid_mem_attrs;
 		tsx_attr = adl_hybrid_tsx_attrs;
 		extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
-			mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
+			nvl_hybrid_extra_attr_rtm : nvl_hybrid_extra_attr;
 
 		/* Initialize big core specific PerfMon capabilities.*/
 		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];