FAILED: patch "[PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround" failed to apply to 7.2-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 7.2-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-7.2.y
git checkout FETCH_HEAD
git cherry-pick -x 45f7304679875eb000d67e194090ee7abd05c89c
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026100500-widget-handcart-8d85@gregkh' --subject-prefix 'PATCH 7.2.y' 'HEAD^..'
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 45f7304679875eb000d67e194090ee7abd05c89c Mon Sep 17 00:00:00 2001
From: Beata Michalska <[email protected]>
Date: Thu, 1 Oct 2026 11:00:32 +0200
Subject: [PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround
Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency.
The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source.
The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround.
Documentation/arch/arm64/silicon-errata.rst +2 -0
@@ -174,6 +174,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #1502854 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
arch/arm64/Kconfig +22 -0
@@ -1081,6 +1081,28 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool
arch/arm64/kernel/cpu_errata.c +4 -0
@@ -389,6 +389,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = {#ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 +/* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2),#endif {} };
arch/arm64/kernel/topology.c +5 -4
@@ -395,10 +395,11 @@ static void cpu_read_corecnt(void *val)static void cpu_read_constcnt (void *val) {/* -* Return 0 if the current CPU is affected by erratum 2457168. A value -* of 0 is also returned if the current CPU does not support AMUs or if -* the counter is disabled. A return value of 0 at counter read is -* properly handled as an error case by the users of the counter. +* Return 0 if the current CPU is affected by a HW erratum. +* A value of 0 is also returned if the current CPU does not +* support AMUs or if the counter is disabled. A return +* value of 0 at counter read is properly handled as an error +* case by the users of the counter. */ *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ) ?0UL :read_constcnt ();
Sasha Levin
maintainerPATCH 1/2 arm64: errata: Factor out broken AMU const counter cap
From: Beata Michalska <[email protected]>
[ Upstream commit 573371caf7aea8582212da81dcead2c3f48fac4b ]
Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites.
Omit the comment update in amu_read_core_const_ctrs(), since paired CPPC FFH counter reads are not implemented here. Keep the capability rename in the existing counter-read and initialization paths, together with the shared MIDR range list needed by the additional erratum.
Stable-dep-of: 45f730467987 ("arm64: errata: Add Cortex-A725 erratum 3821522 workaround")
--- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 25 insertions(+), 9 deletions(-)
arch/arm64/Kconfig +8 -0
@@ -1017,9 +1017,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168.
arch/arm64/kernel/cpu_errata.c +14 -6
@@ -377,6 +377,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { };#endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 +/* Cortex-A510 r0p0-r1p1 */ +MIDR_RANGE (MIDR_CORTEX_A510 ,0 ,0 ,1 ,1 ), +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ +#ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX),
@@ -904,14 +914,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) },#endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923
arch/arm64/kernel/cpufeature.c +1 -1
@@ -2087,7 +2087,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)cpumask_set_cpu (smp_processor_id (), &amu_cpus);/* 0 reference values signal broken/disabled counters */ -if (!this_cpu_has_cap (ARM64_WORKAROUND_2457168 )) +if (!this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ))update_freq_counters_refs (); } }
arch/arm64/kernel/topology.c +1 -1
@@ -390,7 +390,7 @@ static void cpu_read_constcnt(void *val)* the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_2457168 ) ? + *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ) ?0UL :read_constcnt (); }
arch/arm64/tools/cpucaps +1 -1
@@ -103,7 +103,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_4193714
@@ -128,3 +127,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNT
Signature · 1 line
2.53.0
Sasha Levin
maintainerPATCH 2/2 arm64: errata: Add Cortex-A725 erratum 3821522 workaround
From: Beata Michalska <[email protected]>
[ Upstream commit 45f7304679875eb000d67e194090ee7abd05c89c ]
Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency.
The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source.
The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround.
--- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 22 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 4 ++++ arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 33 insertions(+), 4 deletions(-)
Documentation/arch/arm64/silicon-errata.rst +2 -0
@@ -174,6 +174,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #1502854 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
arch/arm64/Kconfig +22 -0
@@ -1058,6 +1058,28 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool
arch/arm64/kernel/cpu_errata.c +4 -0
@@ -382,6 +382,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = {#ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 +/* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2),#endif {} };
arch/arm64/kernel/topology.c +5 -4
@@ -385,10 +385,11 @@ static void cpu_read_corecnt(void *val)static void cpu_read_constcnt (void *val) {/* -* Return 0 if the current CPU is affected by erratum 2457168. A value -* of 0 is also returned if the current CPU does not support AMUs or if -* the counter is disabled. A return value of 0 at counter read is -* properly handled as an error case by the users of the counter. +* Return 0 if the current CPU is affected by a HW erratum. +* A value of 0 is also returned if the current CPU does not +* support AMUs or if the counter is disabled. A return +* value of 0 at counter read is properly handled as an error +* case by the users of the counter. */ *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ) ?0UL :read_constcnt ();
Signature · 1 line
2.53.0
Re: [PATCH 7.2.y 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround
LGTM
Thank you!
---
BR
Beata
Quoted 119 lines · Sasha Levin
From: Beata Michalska <[email protected]>
[ Upstream commit
45f7304679875eb000d67e194090ee7abd05c89c]Cortex-A725 erratum 3821522 affects the
CNT_CYCLESevent, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency.The
AMEVCNTR01_EL0counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source.The erratum can also affect PMUv3 users of the
CNT_CYCLESevent, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround.Signed-off-by Beata Michalska <[email protected]>Reviewed-by Vladimir Murzin <[email protected]>Signed-off-by Will Deacon <[email protected]>Signed-off-by Sasha Levin <[email protected]>--- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 22 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 4 ++++ arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 33 insertions(+), 4 deletions(-)Documentation/arch/arm64/silicon-errata.rst +2
-0@@ -174,6 +174,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #1502854 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |arch/arm64/Kconfig +22
-0@@ -1058,6 +1058,28 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD boolarch/arm64/kernel/cpu_errata.c +4
-0@@ -382,6 +382,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = {#ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 +/* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2),#endif {} };arch/arm64/kernel/topology.c +5
-4@@ -385,10 +385,11 @@ static void cpu_read_corecnt(void *val)static void cpu_read_constcnt (void *val) {/* -* Return 0 if the current CPU is affected by erratum 2457168. A value -* of 0 is also returned if the current CPU does not support AMUs or if -* the counter is disabled. A return value of 0 at counter read is -* properly handled as an error case by the users of the counter. +* Return 0 if the current CPU is affected by a HW erratum. +* A value of 0 is also returned if the current CPU does not +* support AMUs or if the counter is disabled. A return +* value of 0 at counter read is properly handled as an error +* case by the users of the counter. */ *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ) ?0UL :read_constcnt ();Signature · 1 line
2.53.0
Re: [PATCH 7.2.y 1/2] arm64: errata: Factor out broken AMU const counter cap
In reply to Sasha LevinHi Sasha,
Was just about to deal with the backports.
All looks good.
Thank you for that!
---
BR
Beata
Quoted 136 lines · Sasha Levin
From: Beata Michalska <[email protected]>
[ Upstream commit
573371caf7aea8582212da81dcead2c3f48fac4b]Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites.
Signed-off-by Beata Michalska <[email protected]>Reviewed-by Vladimir Murzin <[email protected]>Signed-off-by Will Deacon <[email protected]>Omit the comment update in
amu_read_core_const_ctrs(), since paired CPPC FFH counter reads are not implemented here. Keep the capability rename in the existing counter-read and initialization paths, together with the shared MIDR range list needed by the additional erratum.Stable-dep-of:
45f730467987("arm64: errata: Add Cortex-A725 erratum 3821522 workaround")Signed-off-by Sasha Levin <[email protected]>--- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 25 insertions(+), 9 deletions(-)arch/arm64/Kconfig +8
-0@@ -1017,9 +1017,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168.arch/arm64/kernel/cpu_errata.c +14
-6@@ -377,6 +377,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { };#endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 +/* Cortex-A510 r0p0-r1p1 */ +MIDR_RANGE (MIDR_CORTEX_A510 ,0 ,0 ,1 ,1 ), +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ +#ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX),@@ -904,14 +914,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) },#endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923arch/arm64/kernel/cpufeature.c +1
-1@@ -2087,7 +2087,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)cpumask_set_cpu (smp_processor_id (), &amu_cpus);/* 0 reference values signal broken/disabled counters */ -if (!this_cpu_has_cap (ARM64_WORKAROUND_2457168 )) +if (!this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ))update_freq_counters_refs (); } }arch/arm64/kernel/topology.c +1
-1@@ -390,7 +390,7 @@ static void cpu_read_constcnt(void *val)* the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_2457168 ) ? + *(u64 *)val =this_cpu_has_cap (ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT ) ?0UL :read_constcnt (); }arch/arm64/tools/cpucaps +1
-1@@ -103,7 +103,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_4193714@@ -128,3 +127,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNTSignature · 1 line
2.53.0