riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram

PATCH Superseded Hung-Chun Tseng 3 participants 7 messages Oct 12 – Oct 15

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Device tree bindings RISC-V RISC-V SpacemiT SoC Support

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Hung-Chun Tseng

author

2026-10-12 23:56 UTC #0 lore raw

cover riscv: dts: spacemit: mark K1 boot nodes bootph-pre-ram

A bootloader SPL on the SpacemiT K1 runs from SRAM and needs a handful of nodes before DRAM is up: the root clocks and clock controllers, the console UART, the boot media (SD, eMMC, QSPI NOR), the board EEPROM used to identify the board, and the PMIC rails it programs before DRAM training. Today mainline U-Boot carries the bootph-pre-ram tags for these in per-board -u-boot.dtsi files.

When I sent a U-Boot patch adding another such file for the Milk-V Jupiter, E Shattow asked for the tags to go upstream first, so every K1 board gets them and the U-Boot overlays can shrink [1]. Earlier there was no working mainline SPL for K1 to justify them; there is now.

Patch 1 tags the SoC nodes in k1.dtsi. Patch 2 tags the board-specific EEPROM, PMIC rails and SPI NOR on the boards that have them. The set of nodes matches what the mainline U-Boot SPL tags for the BPI-F3 and MusePi Pro.

Testing: all K1 DTBs build, and dtbs_check is clean for them with and without this series. I have not run an SPL built from these trees on hardware. On a Milk-V Jupiter running Linux I checked that the EEPROM, PMIC and SPI NOR answer at the addresses described.

[1] https://lore.kernel.org/u-boot/[email protected]/

Hung-Chun Tseng (2):
riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram
riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

 arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi |  7 +++++++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts   |  7 +++++++
 arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts |  8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts    |  8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts  |  5 +++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts  |  6 ++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi              | 12 ++++++++++++
 7 files changed, 53 insertions(+)

Signature · 1 line

2.43.0

Hung-Chun Tseng

author

2026-10-12 23:56 UTC #1 lore raw

PATCH 1/2 riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram

A bootloader SPL that follows the K1 BootROM runs from SRAM before DRAM is up. It needs the root clocks, the clock and reset controllers, the console UART, and the boot media controllers: SD (sdhci0), eMMC and QSPI NOR. Mark these nodes bootph-pre-ram so an SPL can use the upstream device tree as is, instead of carrying the tags in per-board overlays.

These are the SoC nodes that the mainline U-Boot SPL for K1 currently tags in its board -u-boot.dtsi files.

Assisted-by claude-opus-5-5 dtbs_check

Signed-off-by Hung-Chun Tseng <[email protected]>

---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/spacemit/k1.dtsi +12 -0

index 3fabfd341..8ca98d15a 100644
@@ -322,6 +322,7 @@ cluster1_l2_cache: l2-cache1 {
 	clocks {
 		vctcxo_1m: clock-1m {
 			compatible = "fixed-clock";
+			bootph-pre-ram;
 			clock-frequency = <1000000>;
 			clock-output-names = "vctcxo_1m";
 			#clock-cells = <0>;

@@ -329,6 +330,7 @@ vctcxo_1m: clock-1m {
 
 		vctcxo_24m: clock-24m {
 			compatible = "fixed-clock";
+			bootph-pre-ram;
 			clock-frequency = <24000000>;
 			clock-output-names = "vctcxo_24m";
 			#clock-cells = <0>;

@@ -336,6 +338,7 @@ vctcxo_24m: clock-24m {
 
 		vctcxo_3m: clock-3m {
 			compatible = "fixed-clock";
+			bootph-pre-ram;
 			clock-frequency = <3000000>;
 			clock-output-names = "vctcxo_3m";
 			#clock-cells = <0>;

@@ -343,6 +346,7 @@ vctcxo_3m: clock-3m {
 
 		osc_32k: clock-32k {
 			compatible = "fixed-clock";
+			bootph-pre-ram;
 			clock-frequency = <32768>;
 			clock-output-names = "osc_32k";
 			#clock-cells = <0>;

@@ -586,6 +590,7 @@ i2c5: i2c@d4013800 {
 		syscon_apbc: system-controller@d4015000 {
 			compatible = "spacemit,k1-syscon-apbc";
 			reg = <0x0 0xd4015000 0x0 0x1000>;
+			bootph-pre-ram;
 			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
 				 <&vctcxo_24m>;
 			clock-names = "osc", "vctcxo_1m", "vctcxo_3m",

@@ -857,6 +862,7 @@ pwm19: pwm@d4022c00 {
 		syscon_mpmu: system-controller@d4050000 {
 			compatible = "spacemit,k1-syscon-mpmu";
 			reg = <0x0 0xd4050000 0x0 0x209c>;
+			bootph-pre-ram;
 			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
 				 <&vctcxo_24m>;
 			clock-names = "osc", "vctcxo_1m", "vctcxo_3m",

@@ -869,6 +875,7 @@ syscon_mpmu: system-controller@d4050000 {
 		pll: clock-controller@d4090000 {
 			compatible = "spacemit,k1-pll";
 			reg = <0x0 0xd4090000 0x0 0x1000>;
+			bootph-pre-ram;
 			clocks = <&vctcxo_24m>;
 			spacemit,mpmu = <&syscon_mpmu>;
 			#clock-cells = <1>;

@@ -877,6 +884,7 @@ pll: clock-controller@d4090000 {
 		syscon_apmu: system-controller@d4282800 {
 			compatible = "spacemit,k1-syscon-apmu";
 			reg = <0x0 0xd4282800 0x0 0x400>;
+			bootph-pre-ram;
 			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
 				 <&vctcxo_24m>;
 			clock-names = "osc", "vctcxo_1m", "vctcxo_3m",

@@ -956,6 +964,7 @@ uart0: serial@d4017000 {
 				compatible = "spacemit,k1-uart",
 					     "intel,xscale-uart";
 				reg = <0x0 0xd4017000 0x0 0x100>;
+				bootph-pre-ram;
 				clocks = <&syscon_apbc CLK_UART0>,
 					 <&syscon_apbc CLK_UART0_BUS>;
 				clock-names = "core", "bus";

@@ -1085,6 +1094,7 @@ qspi: spi@d420c000 {
 				reg = <0x0 0xd420c000 0x0 0x1000>,
 				      <0x0 0xb8000000 0x0 0xc00000>;
 				reg-names = "QuadSPI", "QuadSPI-memory";
+				bootph-pre-ram;
 				clocks = <&syscon_apmu CLK_QSPI_BUS>,
 					 <&syscon_apmu CLK_QSPI>;
 				clock-names = "qspi_en", "qspi";

@@ -1328,6 +1338,7 @@ usb_dwc3: usb@c0a00000 {
 			sdhci0: mmc@d4280000 {
 				compatible = "spacemit,k1-sdhci";
 				reg = <0x0 0xd4280000 0x0 0x200>;
+				bootph-pre-ram;
 				clocks = <&syscon_apmu CLK_SDH_AXI>,
 					 <&syscon_apmu CLK_SDH0>;
 				clock-names = "core", "io";

@@ -1341,6 +1352,7 @@ sdhci0: mmc@d4280000 {
 			emmc: mmc@d4281000 {
 				compatible = "spacemit,k1-sdhci";
 				reg = <0x0 0xd4281000 0x0 0x200>;
+				bootph-pre-ram;
 				clocks = <&syscon_apmu CLK_SDH_AXI>,
 					 <&syscon_apmu CLK_SDH2>;
 				clock-names = "core", "io";

Signature · 1 line

2.43.0

[email protected]

AI review

2026-10-13 00:04 UTC #2 lore raw

Re: [PATCH 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] dt: spacemit: k1: boot media incorrectly marked bootph-pre-ram in SoC dtsi --

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt: spacemit: k1: boot media incorrectly marked bootph-pre-ram in SoC dtsi --

commit 8f0e131a27a4e9b047773ff808813b281fae2061
Author: Hung-Chun Tseng <[email protected]>

riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram

This commit marks several K1 SoC nodes with the bootph-pre-ram tag to allow a U-Boot SPL to use the upstream device tree directly. It adds the tag to clocks, system controllers, UART, and boot media controllers (SD, eMMC, and QSPI).

Quoted 4 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +0 -0
index 3fabfd34114b2..8ca98d15a117a 100644

[ ... ]

arch/riscv/boot/dts/spacemit/k1.dtsi qspi: spi@d420c000 { · line 1097

Quoted 5 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +1 -0

@@ -1085,6 +1094,7 @@ qspi: spi@d420c000 {
 				reg = <0x0 0xd420c000 0x0 0x1000>,
 				      <0x0 0xb8000000 0x0 0xc00000>;
 				reg-names = "QuadSPI", "QuadSPI-memory";
+				bootph-pre-ram;

[Severity: Low]
Does adding the bootph-pre-ram tag globally to the QSPI boot media controller in the SoC dtsi prevent individual boards from excluding the QSPI driver from their SPL if they don't use it for early boot?

When a board includes k1.dtsi and enables a peripheral like QSPI for OS-level storage but does not use it as the early boot medium, this inherited tag forces the QSPI driver and node into the SPL anyway.

This unnecessarily inflates the U-Boot SPL binary size and increases SRAM memory pressure.

Standard devicetree practice mandates that boot media phase tags be defined in per-board .dts files or -u-boot.dtsi overlays corresponding to the actual boot interfaces wired and used by that specific board.

Quoted 3 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +0 -0

 				clocks = <&syscon_apmu CLK_QSPI_BUS>,
 					 <&syscon_apmu CLK_QSPI>;
 				clock-names = "qspi_en", "qspi";

[ ... ]

arch/riscv/boot/dts/spacemit/k1.dtsi usb_dwc3: usb@c0a00000 { · line 1341

Quoted 5 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +1 -0

@@ -1328,6 +1338,7 @@ usb_dwc3: usb@c0a00000 {
 			sdhci0: mmc@d4280000 {
 				compatible = "spacemit,k1-sdhci";
 				reg = <0x0 0xd4280000 0x0 0x200>;
+				bootph-pre-ram;

[Severity: Low]
Could this global bootph-pre-ram tag force the SD card controller driver into the SPL even for boards that do not use it as their early boot medium?

arch/riscv/boot/dts/spacemit/k1.dtsi sdhci0: mmc@d4280000 { · line 1355

Quoted 8 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +1 -0

 				clocks = <&syscon_apmu CLK_SDH_AXI>,
 					 <&syscon_apmu CLK_SDH0>;
 				clock-names = "core", "io";

@@ -1341,6 +1352,7 @@ sdhci0: mmc@d4280000 {
 			emmc: mmc@d4281000 {
 				compatible = "spacemit,k1-sdhci";
 				reg = <0x0 0xd4281000 0x0 0x200>;
+				bootph-pre-ram;

[Severity: Low]
Does adding this tag to the eMMC controller in the SoC dtsi cause the same issue of forcing unnecessary drivers into the SPL for boards that boot from other media?

Quoted 3 lines

arch/riscv/boot/dts/spacemit/k1.dtsi +0 -0

 				clocks = <&syscon_apmu CLK_SDH_AXI>,
 					 <&syscon_apmu CLK_SDH2>;
 				clock-names = "core", "io";

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1

Hung-Chun Tseng

author

2026-10-12 23:56 UTC #3 lore raw

PATCH 2/2 riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

In reply to Hung-Chun Tseng

On K1 boards an SPL reads the board EEPROM (0x50 on i2c2) to identify the board, and before DRAM training it programs the P1 PMIC (0x41 on i2c8) rails buck1, buck3 and aldo1. Boards that boot from SPI NOR also need the flash on QSPI.

Mark these board peripherals, and the I2C buses they sit on, bootph-pre-ram on the boards that have them.

Assisted-by claude-opus-5-5 dtbs_check

Signed-off-by Hung-Chun Tseng <[email protected]>

---
 arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 7 +++++++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts   | 7 +++++++
 arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts    | 8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts  | 5 +++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts  | 6 ++++++
 6 files changed, 41 insertions(+)

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +7 -0

index 81c40df2a..6269d2ba7 100644
@@ -64,6 +64,7 @@ &pdma {
 };
 
 &i2c2 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_0_cfg>;
 	status = "okay";

@@ -71,6 +72,7 @@ &i2c2 {
 	eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
+		bootph-pre-ram;
 		vcc-supply = <&buck3_1v8>;
 		pagesize = <16>;
 		read-only;

@@ -93,6 +95,7 @@ serial-number {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8_cfg>;
 	status = "okay";

@@ -100,6 +103,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

@@ -113,6 +117,7 @@ pmic@41 {
 
 		regulators {
 			buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -127,6 +132,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -155,6 +161,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +7 -0

index 58035d886..e74505984 100644
@@ -187,6 +187,7 @@ &qspi {
 };
 
 &i2c2 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c2_0_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -194,6 +195,7 @@ &i2c2 {
 	eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
+		bootph-pre-ram;
 		vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */
 		pagesize = <16>;
 		read-only;

@@ -216,6 +218,7 @@ serial-number {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c8_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -223,6 +226,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

@@ -236,6 +240,7 @@ pmic@41 {
 
 		regulators {
 			buck1_0v9: buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -250,6 +255,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -278,6 +284,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +8 -0

index 635e95aad..406b7ca16 100644
@@ -201,6 +201,7 @@ &pdma {
 };
 
 &i2c2 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c2_0_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -208,6 +209,7 @@ &i2c2 {
 	eeprom@50 {
 		compatible = "atmel,24c04";
 		reg = <0x50>;
+		bootph-pre-ram;
 		vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */
 		pagesize = <16>;
 		read-only;

@@ -223,6 +225,7 @@ product-name {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c8_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -230,6 +233,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

@@ -243,6 +247,7 @@ pmic@41 {
 
 		regulators {
 			buck1_0v9: buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -257,6 +262,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -285,6 +291,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

@@ -386,6 +393,7 @@ &qspi {
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
+		bootph-pre-ram;
 		spi-max-frequency = <26500000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;

arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +8 -0

index 246f8f2ab..0531bd003 100644
@@ -127,6 +127,7 @@ &pdma {
 };
 
 &i2c2 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c2_0_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -134,6 +135,7 @@ &i2c2 {
 	eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
+		bootph-pre-ram;
 		vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */
 		pagesize = <8>;
 		read-only;

@@ -159,6 +161,7 @@ num-macs {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-0 = <&i2c8_cfg>;
 	pinctrl-names = "default";
 	status = "okay";

@@ -166,6 +169,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

@@ -179,6 +183,7 @@ pmic@41 {
 
 		regulators {
 			buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -193,6 +198,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -221,6 +227,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

@@ -320,6 +327,7 @@ &qspi {
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
+		bootph-pre-ram;
 		spi-max-frequency = <26500000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;

arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +5 -0

index 2d1ba34cb..8e9bbbeb1 100644
@@ -113,6 +113,7 @@ rgmii1: phy@1 {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8_cfg>;
 	status = "okay";

@@ -120,6 +121,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&vcc4v0>;
 		vin2-supply = <&vcc4v0>;

@@ -133,6 +135,7 @@ pmic@41 {
 
 		regulators {
 			buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -147,6 +150,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -175,6 +179,7 @@ buck6 {
 			};
 
 			aldo1_3v3: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +6 -0

index b907a1396..857b4ebe3 100644
@@ -143,6 +143,7 @@ &pdma {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8_cfg>;
 	status = "okay";

@@ -150,6 +151,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&vcc4v0>;
 		vin2-supply = <&vcc4v0>;

@@ -163,6 +165,7 @@ pmic@41 {
 
 		regulators {
 			buck1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -177,6 +180,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -205,6 +209,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

@@ -298,6 +303,7 @@ &qspi {
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
+		bootph-pre-ram;
 		spi-max-frequency = <26500000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;

Signature · 1 line

2.43.0

[email protected]

AI review

2026-10-13 00:08 UTC #4 lore raw

Re: [PATCH 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] dts: missing bootph-pre-ram on pinctrl and regulator dependencies for SPL --

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: missing bootph-pre-ram on pinctrl and regulator dependencies for SPL --

commit 76ae02e32445137eb75156ac64fdd5ee85cb4ef0
Author: Hung-Chun Tseng <[email protected]>

riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

This patch adds the bootph-pre-ram property to I2C buses, board EEPROMs, PMICs, and QSPI flashes on various SpacemiT K1 boards. These additions enable U-Boot's SPL to access the devices during the early boot phase before DRAM training.

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi serial-number { · line 101

Quoted 12 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +1 -0

index 81c40df2a3663..6269d2ba78ed0 100644
@@ -93,6 +95,7 @@ serial-number {
 };
 
 &i2c8 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8_cfg>;
 	status = "okay";

[Severity: Medium]
Will this I2C pinmux setup fail in the SPL?

The I2C bus is marked for SPL, but the pin configuration node i2c8_cfg in k1-pinctrl.dtsi and the base pinctrl controller pinctrl@d401e000 in k1.dtsi both lack the bootph-pre-ram property.

U-Boot's fdtgrep will strip these unmarked nodes from the SPL device tree, which will prevent the I2C pins from being multiplexed correctly.

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi &i2c8 { · line 109

Quoted 8 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +1 -0

@@ -100,6 +103,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

[Severity: Medium]
Will this PMIC probe fail in the SPL phase?

The PMIC relies on the reg_vcc_4v fixed regulator as its input supply, but the reg_vcc_4v node was not marked with bootph-pre-ram.

Without this property, the fixed regulator will be excluded from the SPL device tree, leading to dangling phandles and early boot probe failures for the PMIC.

Quoted 4 lines

arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +0 -0
index 635e95aad14a5..406b7ca163db8 100644

[ ... ]

arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts &qspi { · line 399

Quoted 8 lines

arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +1 -0

@@ -386,6 +393,7 @@ &qspi {
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
+		bootph-pre-ram;
 		spi-max-frequency = <26500000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;

[Severity: Medium]
Will this flash fail to operate during early boot?

The flash@0 node uses buck4_3v3 as its vcc-supply. While buck1 and buck3 were marked with bootph-pre-ram in this patch, buck4_3v3 was omitted.

The missing property on buck4_3v3 will cause the supply node to be stripped from the SPL device tree, breaking flash access before RAM is initialized.

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2

Yixun Lan

maintainer

2026-10-15 07:46 UTC #5 lore raw

Re: [PATCH 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

In reply to Hung-Chun Tseng

Hi Hung-Chun,

Have two minor comments, see below

Quoted 40 lines · Hung-Chun Tseng

On K1 boards an SPL reads the board EEPROM (0x50 on i2c2) to identify the board, and before DRAM training it programs the P1 PMIC (0x41 on i2c8) rails buck1, buck3 and aldo1. Boards that boot from SPI NOR also need the flash on QSPI.
Mark these board peripherals, and the I2C buses they sit on, bootph-pre-ram on the boards that have them.
Assisted-by claude-opus-5-5 dtbs_check
Signed-off-by Hung-Chun Tseng <[email protected]>
---
 arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 7 +++++++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts   | 7 +++++++
 arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts    | 8 ++++++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts  | 5 +++++
 arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts  | 6 ++++++
 6 files changed, 41 insertions(+)
arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +2 -0
index 81c40df2a..6269d2ba7 100644
@@ -64,6 +64,7 @@ &pdma {
 };
 
 &i2c2 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_0_cfg>;
 	status = "okay";
@@ -71,6 +72,7 @@ &i2c2 {
 	eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
+		bootph-pre-ram;
 		vcc-supply = <&buck3_1v8>;
 		pagesize = <16>;
 		read-only;

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi serial-number { · line 98

Quoted 4 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +1 -0
@@ -93,6 +95,7 @@ serial-number {
 };
 
 &i2c8 {
+	bootph-pre-ram;

We could move this to dtsi file, since all board share same design which use i2c8 for connecting to pmic, the reward would be that we no longer need to carry this property all over board dts file.. similar we could do for "i2c2", but I noticed k1-orangepi-rv2/r2s have no eeprom enabled..

Quoted 12 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +1 -0

 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8_cfg>;
 	status = "okay";

@@ -100,6 +103,7 @@ &i2c8 {
 	pmic@41 {
 		compatible = "spacemit,p1";
 		reg = <0x41>;
+		bootph-pre-ram;
 		interrupts = <64>;
 		vin1-supply = <&reg_vcc_4v>;
 		vin2-supply = <&reg_vcc_4v>;

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi pmic@41 { · line 120

Quoted 4 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +1 -0
@@ -113,6 +117,7 @@ pmic@41 {
 
 		regulators {
 			buck1 {
+				bootph-pre-ram;

U-Boot also carry "regulator-name" for this node, we probably could also merge it here, but could do it in another patch if want to limit this patch to "pre-ram" change only

Quoted 19 lines

arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +2 -0

 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1050000>;
 				regulator-ramp-delay = <5000>;

@@ -127,6 +132,7 @@ buck2 {
 			};
 
 			buck3_1v8: buck3 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-ramp-delay = <5000>;

@@ -155,6 +161,7 @@ buck6 {
 			};
 
 			aldo1: aldo1 {
+				bootph-pre-ram;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <3400000>;
 				regulator-boot-on;

Signature · 1 line

Yixun Lan (dlan)

Hung-Chun Tseng

author

2026-10-15 12:15 UTC #6 lore raw

Re: [PATCH 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram

Hi Yixun,

Thanks for the review.

Quoted 8 lines · Yixun Lan

Review
Quoted 2 lines
&i2c8 {
(quoted diff) +1 -0
+	bootph-pre-ram;
We could move this to dtsi file, since all board share same design which use i2c8 for connecting to pmic, the reward would be that we no longer need to carry this property all over board dts file.. similar we could do for "i2c2", but I noticed k1-orangepi-rv2/r2s have no eeprom enabled..

Agreed, v2 will tag i2c8 in k1.dtsi. I'll keep i2c2 in the board files, as the OrangePi RV2 and R2S have no EEPROM.

Quoted 6 lines

Review
Quoted 2 lines
			buck1 {
(quoted diff) +1 -0
+				bootph-pre-ram;
U-Boot also carry "regulator-name" for this node, we probably could also merge it here, but could do it in another patch if want to limit this patch to "pre-ram" change only

I'd prefer a separate patch for that, to keep this one about the bootph tags. The U-Boot K1 SPL looks the rails up by name ("vdd_core", "vdd_1v8", "vdd_1v8_mmc"), so once the names are upstream, U-Boot can drop the overrides in its -u-boot.dtsi files.

Thanks,
Hung-Chun