iio: adc: add TI ADS1299

new file mode 100644
index 000000000..a8966cd07
@@ -0,0 +1,221 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1299.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS1299 biopotential analog front-end
+
+maintainers:
+  - Stephan Costa Barros <[email protected]>
+
+description: |
+  Texas Instruments ADS1299 family: low-noise, 24-bit, simultaneous-sampling
+  biopotential (EEG) analog front-ends with an SPI interface. The ADS1299 has
+  eight channels, the ADS1299-6 six and the ADS1299-4 four.
+
+  Each channel has its own programmable gain amplifier and a multiplexer that
+  can select the electrode inputs, a shorted input, the internal test signal,
+  the supply or the temperature sensor. The part also provides lead-off
+  detection and a bias drive amplifier for the driven reference electrode.
+
+  The converter signals a completed conversion on its DRDY output and is read
+  over SPI in mode 1 (CPOL=0, CPHA=1).
+
+  Several converters can share one SPI bus in two ways. In cascaded mode each
+  has its own chip select and its own node; one of them can drive its internal
+  oscillator out of its CLK pin (#clock-cells) for the others to use as their
+  external clock. In daisy-chain mode they share the chip select and DIN, the
+  DOUT of each one feeds the DAISY_IN of the one before it, and the chain is a
+  single node with #daisy-chained-devices. A daisy chain shares DIN, so every
+  register write reaches every device: the devices run with one configuration
+  and from one external clock, and the bias drive amplifier cannot be used.
+
+  https://www.ti.com/lit/gpn/ads1299
+
+properties:
+  compatible:
+    enum:
+      - ti,ads1299
+      - ti,ads1299-4
+      - ti,ads1299-6
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description:
+      The DRDY output of the converter, asserted low when a conversion is
+      ready to be read.
+
+  reset-gpios:
+    maxItems: 1
+    description: The active-low RESET input of the converter.
+
+  powerdown-gpios:
+    maxItems: 1
+    description:
+      The active-low PWDN input.
+
+  clocks:
+    maxItems: 1
+    description:
+      External clock on the CLK pin, used when the CLKSEL pin selects an
+      external clock. Omit when the part runs from its internal oscillator.
+
+  clock-names:
+    const: clk
+
+  '#clock-cells':
+    const: 0
+    description:
+      The CLK pin as a clock output, for a part whose CLKSEL pin selects the
+      internal oscillator.
+
+  clock-output-names:
+    maxItems: 1
+
+  gpio-controller:
+    description:
+      GPIO1 to GPIO4 are wired for use as general-purpose pins. Omit when they
+      are tied to DGND, as the datasheet asks of unused ones, so that no pin
+      tied to ground can be driven as an output.
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-line-names:
+    minItems: 1
+    maxItems: 4
+
+  '#daisy-chained-devices':
+    description:
+      Number of converters in the daisy chain, all of the type the compatible
+      names. Their channels are reported in chain order, the device whose DOUT
+      reaches the host first.
+    minimum: 1
+    maximum: 8
+    default: 1
+
+  avdd-supply:
+    description: Analog supply.
+
+  dvdd-supply:
+    description: Digital supply.
+
+  vref-supply:
+    description:
+      External voltage reference on VREFP. Omit to use the internal 4.5 V
+      reference.
+
+  biasref-supply:
+    description:
+      External voltage on the BIASREF pin, the reference of the bias drive
+      amplifier. Omit to have the part generate (AVDD + AVSS) / 2.
+
+  spi-cpha: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - avdd-supply
+  - spi-cpha
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+  - if:
+      required:
+        - '#clock-cells'
+    then:
+      properties:
+        clocks: false
+  - if:
+      required:
+        - '#daisy-chained-devices'
+      properties:
+        '#daisy-chained-devices':
+          minimum: 2
+    then:
+      required:
+        - clocks
+      properties:
+        '#clock-cells': false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        adc@0 {
+            compatible = "ti,ads1299";
+            reg = <0>;
+            spi-max-frequency = <4000000>;
+            spi-cpha;
+            interrupt-parent = <&gpio1>;
+            interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+            reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+            powerdown-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+            avdd-supply = <&reg_avdd>;
+            dvdd-supply = <&reg_dvdd>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            gpio-line-names = "ADC_GPIO1", "ADC_GPIO2", "", "STATUS_LED";
+        };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    /* Cascaded: the first converter clocks the second */
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        adc0: adc@0 {
+            compatible = "ti,ads1299";
+            reg = <0>;
+            spi-cpha;
+            interrupt-parent = <&gpio1>;
+            interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+            avdd-supply = <&reg_avdd>;
+            #clock-cells = <0>;
+        };
+
+        adc@1 {
+            compatible = "ti,ads1299";
+            reg = <1>;
+            spi-cpha;
+            interrupt-parent = <&gpio1>;
+            interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+            avdd-supply = <&reg_avdd>;
+            clocks = <&adc0>;
+            clock-names = "clk";
+        };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    /* Daisy chain: three converters, 24 channels, one chip select */
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        adc@0 {
+            compatible = "ti,ads1299";
+            reg = <0>;
+            spi-cpha;
+            interrupt-parent = <&gpio1>;
+            interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+            avdd-supply = <&reg_avdd>;
+            clocks = <&osc_2048k>;
+            clock-names = "clk";
+            #daisy-chained-devices = <3>;
+        };
+    };

index 52024397d..b4a8e4573 100644
@@ -27370,6 +27370,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml
 F:	drivers/iio/adc/ti-ads1018.c
 
+TI ADS1299 ADC DRIVER
+M:	Stephan Costa Barros <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	Documentation/devicetree/bindings/iio/adc/ti,ads1299.yaml
+
 TI ADS7924 ADC DRIVER
 M:	Hugo Villeneuve <[email protected]>
 L:	[email protected]

index b4a8e4573..29dcc2c2b 100644
@@ -27375,6 +27375,7 @@ M:	Stephan Costa Barros <[email protected]>
 L:	[email protected]
 S:	Maintained
 F:	Documentation/devicetree/bindings/iio/adc/ti,ads1299.yaml
+F:	drivers/iio/adc/ti-ads1299.c
 
 TI ADS7924 ADC DRIVER
 M:	Hugo Villeneuve <[email protected]>

index 02de4809a..b9f2d3d6e 100644
@@ -1913,6 +1913,20 @@ config TI_ADS1298
 	  This driver can also be built as a module. If so, the module will be
 	  called ti-ads1298.
 
+config TI_ADS1299
+	tristate "Texas Instruments ADS1299"
+	depends on SPI
+	select IIO_BUFFER
+	select IIO_KFIFO_BUF
+	select REGMAP
+	help
+	  Say yes here to build support for Texas Instruments ADS1299,
+	  ADS1299-6 and ADS1299-4 low-noise 24-bit biopotential (EEG)
+	  analog front-ends.
+
+	  This driver can also be built as a module. If so, the module will be
+	  called ti-ads1299.
+
 config TI_ADS131E08
 	tristate "Texas Instruments ADS131E08"
 	depends on SPI

index 9e82c21db..4bb543b66 100644
@@ -162,6 +162,7 @@ obj-$(CONFIG_TI_ADS112C04) += ti-ads112c04.o
 obj-$(CONFIG_TI_ADS112C14) += ti-ads112c14.o
 obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o
 obj-$(CONFIG_TI_ADS1298) += ti-ads1298.o
+obj-$(CONFIG_TI_ADS1299) += ti-ads1299.o
 obj-$(CONFIG_TI_ADS131E08) += ti-ads131e08.o
 obj-$(CONFIG_TI_ADS131M02) += ti-ads131m02.o
 obj-$(CONFIG_TI_ADS7138) += ti-ads7138.o