MIPS: OCTEON: program L2C_CTL on CNF71XX too
PATCH 1/1 MIPS: OCTEON: program L2C_CTL on CNF71XX too
Since commit bd978130307c ("MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II"), cvmx_helper_initialize_packet_io_global() writes L2C_CTL instead of L2C_CFG, because L2C_CFG does not exist on OCTEON II and writing it hangs a CN6335. The test is OCTEON_CN6XXX, which leaves the CNF71XX - also an OCTEON II, as OCTEON_IS_OCTEON2() and the rest of this file treat it - writing the register that commit says is not there.
Use OCTEON_IS_OCTEON2(). OCTEON III (CN7XXX) still takes the L2C_CFG path, as before: I have no such part and do not know which register it wants.
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Found by the Sashiko review bot on the original series. By inspection
only: I have no CNF71XX board to test on. The Fixes: hash is the one in mips-next.
arch/mips/cavium-octeon/executive/cvmx-helper.c +1 -1
@@ -1028,7 +1028,7 @@ int cvmx_helper_initialize_packet_io_global(void)* to the cores. This avoids conditions where IO blocks might * be starved under very high L2 loads. */ -if (OCTEON_IS_MODEL (OCTEON_CN6XXX )) { +if (OCTEON_IS_OCTEON2 ()) {union cvmx_l2c_ctl l2c_ctl; l2c_ctl.u64 =cvmx_read_csr (CVMX_L2C_CTL );