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dt-bindings: clocks: qcom,gcc-ipq8074: allow CMN PLL bias clocks

PATCH In review Robert Marko 2 participants 3 messages Oct 24 – Oct 26

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Device tree bindings Arm Qualcomm mailing list Common clk Arm Qualcomm support +1 more subsystems
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Robert Marko

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#0 lore raw

PATCH 1/2 dt-bindings: clocks: qcom,gcc-ipq8074: allow CMN PLL bias clocks

CMN PLL in IPQ8074 provides 2 fixed clocks to the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC.

This has a benefit that it avoids doing a global matching by name.

Signed-off-by Robert Marko <[email protected]>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 4 ++++
 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +4 -0
index 00d7df75b3d6..d489c6332e6c 100644
@@ -29,6 +29,8 @@ properties:
       - description: sleep clock
       - description: Gen3 QMP PCIe PHY PIPE clock
       - description: Gen2 QMP PCIe PHY PIPE clock
+      - description: 300 MHz bias clock from CMN PLL
+      - description: 416.5 MHz NSS NoC bias clock from CMN PLL
 
   clock-names:
     items:

@@ -36,6 +38,8 @@ properties:
       - const: sleep_clk
       - const: pcie0_pipe
       - const: pcie1_pipe
+      - const: bias_pll_cc_clk
+      - const: bias_pll_nss_noc_clk
 
 required:
   - compatible
Signature · 1 line
2.56.0
author
#1 lore raw

PATCH 2/2 arm64: dts: qcom: ipq8074: Add CMN PLL

Add the CMN PLL node, it will be used to feed the required fixed clocks to networking subsystem.

CMN PLL provides bias_pll_cc_clk and bias_pll_nss_noc_clk to GCC.

Signed-off-by Robert Marko <[email protected]>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/qcom/ipq8074.dtsi +25 -2
index 75a5ae30d966..8afc63a72144 100644
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h>
 
 / {
 	#address-cells = <2>;

@@ -15,6 +16,12 @@ / {
 	interrupt-parent = <&intc>;
 
 	clocks {
+		ref_48mhz_clk: ref-48mhz-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <48000000>;
+			#clock-cells = <0>;
+		};
+
 		sleep_clk: sleep_clk {
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;

@@ -257,6 +264,18 @@ mdio: mdio@90000 {
 			status = "disabled";
 		};
 
+		cmn_pll: clock-controller@9b000 {
+			compatible = "qcom,ipq8074-cmn-pll";
+			reg = <0x0009b000 0x800>;
+			clocks = <&ref_48mhz_clk>,
+				 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+				 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+			clock-names = "ref", "ahb", "sys";
+			#clock-cells = <1>;
+			assigned-clocks = <&cmn_pll IPQ8074_CMN_PLL_CLK>;
+			assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+		};
+
 		qfprom: efuse@a4000 {
 			compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
 			reg = <0x000a4000 0x2000>;

@@ -369,11 +388,15 @@ gcc: clock-controller@1800000 {
 			clocks = <&xo>,
 				 <&sleep_clk>,
 				 <&pcie_qmp0>,
-				 <&pcie_qmp1>;
+				 <&pcie_qmp1>,
+				 <&cmn_pll IPQ8074_BIAS_PLL_CC_CLK>,
+				 <&cmn_pll IPQ8074_BIAS_PLL_NSS_NOC_CLK>;
 			clock-names = "xo",
 				      "sleep_clk",
 				      "pcie0_pipe",
-				      "pcie1_pipe";
+				      "pcie1_pipe",
+				      "bias_pll_cc_clk",
+				      "bias_pll_nss_noc_clk";
 			#clock-cells = <1>;
 			#power-domain-cells = <1>;
 			#reset-cells = <1>;
Signature · 1 line
2.56.0
#2 lore raw
In reply to Robert Marko
Quoted 4 lines · Robert Marko

CMN PLL in IPQ8074 provides 2 fixed clocks to the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC.

This has a benefit that it avoids doing a global matching by name.

That's ABI break, so at minItems.

Quoted 20 lines
Signed-off-by Robert Marko <[email protected]>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 4 ++++
 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +2 -0
index 00d7df75b3d6..d489c6332e6c 100644
@@ -29,6 +29,8 @@ properties:
       - description: sleep clock
       - description: Gen3 QMP PCIe PHY PIPE clock
       - description: Gen2 QMP PCIe PHY PIPE clock
+      - description: 300 MHz bias clock from CMN PLL
+      - description: 416.5 MHz NSS NoC bias clock from CMN PLL
 
   clock-names:
     items:

Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml properties: · line 42

Quoted 5 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +2 -0
@@ -36,6 +38,8 @@ properties:
       - const: sleep_clk
       - const: pcie0_pipe
       - const: pcie1_pipe
+      - const: bias_pll_cc_clk
+      - const: bias_pll_nss_noc_clk

Drop _clk. Names should represent the input.

Best regards,
Krzysztof