KVM: arm64: Fix PMU handling in pKVM

Hi folks,

Changes since v2 [1]:
- Stop the host's counters with PMCR_EL0.E rather than the individual counter enables. (Marc)

Two fixes and a hardening patch for PMU handling in pKVM, as one series [2].

The first is Vincent's rework of his HPMN fix. It supersedes his earlier posting [3]. Rather than read nr_event_counters through a different accessor, the host copies the hypervisor's kvm_host_data before it's deprivileged, so host_data_ptr() returns what was set up at init. Otherwise, HPMN is 0 and a non-protected guest's event counters don't count.

The second is the non-protected half of Oliver's patch from 2024 [4]. It passes the host's PMU events to the hyp vCPU of a non-protected guest, whose counters otherwise all read 0.

The third covers the protected half. It stops the host's counters while a protected guest runs, so the host can't count the guest's cycles and events. Side channels are outside pKVM's threat model, so it carries no
Fixes: tag.

Based on kvmarm/next (dd0bc00e3e920).

Cheers,
/fuad

[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
[3] https://lore.kernel.org/all/[email protected]/
[4] https://lore.kernel.org/all/[email protected]/

Fuad Tabba (1):
KVM: arm64: Disable host PMU counters for protected guests

Oliver Upton (1):
KVM: arm64: Pass the PMU events to the hyp vCPU of non-protected
guests

Vincent Donnefort (1):
KVM: arm64: Synchronise kvm_host_data before host deprivileging

 arch/arm64/kvm/hyp/nvhe/hyp-main.c | 11 +++++++++++
 arch/arm64/kvm/hyp/nvhe/switch.c   | 24 ++++++++++++++++++++++++
 arch/arm64/kvm/pkvm.c              |  6 ++++++
 3 files changed, 41 insertions(+)

base-commit: dd0bc00e3e9201fd49b62ff9cc07890c89003afe

2.47.3

From: Vincent Donnefort <[email protected]>

When protected mode is enabled, the host is populating and reading the hypervisor copy of kvm_host_data until it is deprivileged. This is an issue for nr_event_counters which is only used by the host to populate mdcr_el2. After deprivileging, it is reading an uninitialised value and sets HPMN to 0, preventing programmable event counters from counting a non-protected guest.

Before the host is entirely deprivileged, copy the entire kvm_host_data content from the hypervisor copy to the host-accessible one.

---
 arch/arm64/kvm/pkvm.c | 6 ++++++
 1 file changed, 6 insertions(+)

index 380dfb1db0be4..58190ff6723d6 100644
@@ -316,6 +316,12 @@ static void __init _kvm_host_prot_finalize(void *arg)
 {
 	int *err = arg;
 
+	/*
+	 * After __pkvm_prot_finalize, access to the hypervisor copy of
+	 * kvm_host_data is lost. Save it into the host-accessible version.
+	 */
+	*this_cpu_ptr(&kvm_host_data) = *this_cpu_ptr_nvhe_sym(kvm_host_data);
+
 	if (WARN_ON(kvm_call_hyp_nvhe(__pkvm_prot_finalize)))
 		WRITE_ONCE(*err, -EINVAL);
 }

2.47.3

From: Oliver Upton <[email protected]>

Before every run, the host records in vcpu->arch.pmu.events which perf counters to disable and enable around guest entry, and __pmu_switch_to_guest() applies them at EL2. Since commit be66e67f1750 ("KVM: arm64: Use the pKVM hyp vCPU structure in handle___kvm_vcpu_run()"), protected mode runs the hyp vCPU instead, and flush_hyp_vcpu() never copies the events into it. So the counters backing a non-protected guest's PMU are never enabled, and every counter the guest reads stays at 0, the cycle counter included. The host's counters that exclude guests keep counting the guest as well.

Copy the events into the hyp vCPU of a non-protected guest on every run. The events only exist with CONFIG_HW_PERF_EVENTS, so the copy is built under it. Like mdcr_el2, they're host-controlled and never reach a protected guest.

[Fuad: non-protected copy only, tested on the hyp vCPU, under
CONFIG_HW_PERF_EVENTS, new message]

---
 arch/arm64/kvm/hyp/nvhe/hyp-main.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

index d715aa942577e..28a292deecb64 100644
@@ -690,6 +690,16 @@ static void sync_debug_state(struct pkvm_hyp_vcpu *hyp_vcpu)
 		host_vcpu->arch.external_debug_state = hyp_vcpu->vcpu.arch.external_debug_state;
 }
 
+#ifdef CONFIG_HW_PERF_EVENTS
+static void flush_pmu_state(struct pkvm_hyp_vcpu *hyp_vcpu)
+{
+	if (!pkvm_hyp_vcpu_is_protected(hyp_vcpu))
+		hyp_vcpu->vcpu.arch.pmu.events = hyp_vcpu->host_vcpu->arch.pmu.events;
+}
+#else
+static void flush_pmu_state(struct pkvm_hyp_vcpu *hyp_vcpu) {}
+#endif
+
 static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu)
 {
 	struct kvm_vcpu *host_vcpu = hyp_vcpu->host_vcpu;

@@ -698,6 +708,7 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu)
 
 	fpsimd_sve_flush();
 	flush_debug_state(hyp_vcpu);
+	flush_pmu_state(hyp_vcpu);
 
 	/*
 	 * If we deal with a non-protected guest and the state is potentially

2.47.3

A protected guest has no PMU, and EL2 clears MDCR_EL2.HPME for it. However, __pkvm_vcpu_load() sets HPMN to cover every event counter, so HPME has no effect and the counters the host has enabled keep counting the guest.

Clear PMCR_EL0.E in the world switch while a protected guest runs, which stops them all. Gate this on system_supports_pmuv3(), as __activate_traps_common() does for PMUSERENR_EL0.

Side channels are outside pKVM's threat model, so this is hardening rather than a fix.

---
 arch/arm64/kvm/hyp/nvhe/switch.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

index 91e1edf40bcd2..003469e85ed46 100644
@@ -175,6 +175,26 @@ static void __pmu_switch_to_host(struct kvm_vcpu *vcpu)
 #define __pmu_switch_to_host(v)		do {} while (0)
 #endif
 
+static u64 __pmu_stop_host_counters(struct kvm_vcpu *vcpu)
+{
+	u64 pmcr;
+
+	if (!vcpu_is_protected(vcpu) || !system_supports_pmuv3())
+		return 0;
+
+	pmcr = read_sysreg(pmcr_el0);
+	if (pmcr & ARMV8_PMU_PMCR_E)
+		write_sysreg(pmcr & ~ARMV8_PMU_PMCR_E, pmcr_el0);
+
+	return pmcr;
+}
+
+static void __pmu_restore_host_counters(u64 pmcr)
+{
+	if (pmcr & ARMV8_PMU_PMCR_E)
+		write_sysreg(pmcr, pmcr_el0);
+}
+
 /*
  * Handler for protected VM MSR, MRS or System instruction execution in AArch64.
  *

@@ -283,6 +303,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 	struct kvm_s2_mmu *mmu;
 	bool pmu_switch_needed;
 	u64 exit_code;
+	u64 host_pmcr;
 
 	/*
 	 * Having IRQs masked via PMR when entering the guest means the GIC

@@ -300,6 +321,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 	guest_ctxt = &vcpu->arch.ctxt;
 
 	pmu_switch_needed = __pmu_switch_to_guest(vcpu);
+	host_pmcr = __pmu_stop_host_counters(vcpu);
 
 	__sysreg_save_state_nvhe(host_ctxt);
 	/*

@@ -384,6 +406,8 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 	if (pmu_switch_needed)
 		__pmu_switch_to_host(vcpu);
 
+	__pmu_restore_host_counters(host_pmcr);
+
 	/* Returning to host will clear PSR.I, remask PMR if needed */
 	if (system_uses_irq_prio_masking())
 		gic_write_pmr(GIC_PRIO_IRQOFF);

2.47.3

Applied to fixes, thanks!

[1/3] KVM: arm64: Synchronise kvm_host_data before host deprivileging

      commit: 9e29ea628848d29eea948200c4357f530b0e1768
[2/3] KVM: arm64: Pass the PMU events to the hyp vCPU of non-protected guests
      commit: 8ee90ca40b10cc040544fdccf24b20115f46aa7d
[3/3] KVM: arm64: Disable host PMU counters for protected guests
      commit: a7dd36f7e381025bdf01d8665bf37167368754c4

Cheers,

	M.

Without deviation from the norm, progress is not possible.