clk: sunxi-ng: a733: preserve system-controller firmware clocks
Subsystems (2)
PATCH 1/1 clk: sunxi-ng: a733: preserve system-controller firmware clocks
System-controller firmware uses the R-domain timer and mailboxes without Linux clock consumers. Disabling these clocks as unused can leave firmware services unavailable. On a Radxa Cubie A7S with vendor boot firmware, the public CCU v6 candidate reaches a Linux shell but stalls at warm reboot.
The public A733 firmware selects the RISC-V platform, reserves R-domain timer0 for delays and enables both main and R-domain mailbox clocks. Retain r-timer0, bus-r-timer, bus-r-riscv, bus-msgbox0 and bus-r-msgbox with CLK_IS_CRITICAL. This keeps their modeled parents enabled as well. Do not change rates, muxes, reset bits or unrelated gate policy.
The controlled tests distinguish the RISC-V bus gate from its separate special clock. They support this set for the tested A7S firmware, without establishing that every flag is independently minimal or that all firmware services are covered. The matching A7S configuration completed repeated warm reboots without clk_ignore_unused or a register-writing helper. Suspend is not qualified by these tests.
Public firmware evidence:
https://github.com/radxa/allwinner-arisc/tree/79086caef1f6d1fb1cf164afb018f6e873fd9910/ar100s
AI assistance: Codex:gpt-6-astra.
---
This is a standalone clock change for the separate A733/Cubie A7S DT v2. It applies to official base d89e1d186ec9271bf78e62771779e9fc03bf0fc3 plus Junhui Liu's four clock-helper patches and A733 CCU v6 (eight):
https://lore.kernel.org/r/[email protected]
https://lore.kernel.org/r/[email protected]
No Fixes tag is assigned to the unmerged CCU input. This does not replace or resubmit Junhui's series. The existing public MBUS_STORE critical flag is not part of this change.
The final A7S integration passed two RAM boots, clock-summary checks and warm reboots with vendor U-Boot 2018.07-17-boot-aw2501-g4c7078cfdf7-dirty. All five retained clocks reported enabled. The Image was built with W=1; the final DTB passed W=2 CHECK_DTBS=y. Earlier tests of the same five-clock change also passed four boots and warm reboots. These are system observations on one board, not proof of each flag's independent minimality or suspend. The DT test used a RAM-only BL31 reservation at 0x48000000/0x01000000.
Final tested Image SHA-256:1ea68cdc5998b584f8a3e62c44a21e506a22a8144c5824d9a8485607a8f2bd09
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 13 +++++++++---- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 3 ++- 2 files changed, 11 insertions(+), 5 deletions(-)
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c +9 -4
@@ -57,11 +57,12 @@ static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", r_apb_parents, 0x010,24 ,3 ,/* mux */ 0); +/* System-controller firmware uses R-domain timer0 for delays. */ static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100,1 ,3 ,/* P */ 4 ,3 ,/* mux */ BIT (0 ),/* gate */ - 0); + CLK_IS_CRITICAL); static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104,1 ,3 ,/* P */ 4, 3, /* mux */
@@ -78,7 +79,8 @@ static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0BIT (0 ),/* gate */ 0); -static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw, 0x11c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", + &r_ahb_clk.common.hw, 0x11c, BIT(0), CLK_IS_CRITICAL);static const struct clk_parent_data r_pwm_parents[] = { { .fw_name ="hosc" },
@@ -108,7 +110,9 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150, 0); static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi", &r_ahb_clk.common.hw, 0x15c, BIT(0), 0); -static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0); +/* Firmware can use this mailbox without a Linux clock consumer. */ +staticSUNXI_CCU_GATE_HW (bus_r_msgbox_clk,"bus-r-msgbox" , + &r_ahb_clk.common.hw,0x17c ,BIT (0 ),CLK_IS_CRITICAL ); static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0", &r_apb1_clk.common.hw, 0x18c, BIT(0), 0); static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1", &r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
@@ -146,8 +150,9 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, "r-riscv", r_riscv_parents, 0x224 ,2 ,/* mux */ BIT (31 ),/* gate */ 0); +/* Firmware runs on the RISC-V core independently of Linux. */ static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw, - 0x21c, BIT(0), 0); + 0x21c, BIT(0), CLK_IS_CRITICAL); static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, "bus-r-riscv-cfg", &r_apb0_clk.common.hw, 0x21c, BIT(1), 0);
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +2 -1
@@ -635,8 +635,9 @@ static SUNXI_CCU_GATE_HWS(bus_dma1_clk, "bus-dma1", ahb_hws, static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, 0x724, BIT(0), 0); +/* Keep the mailbox available to system-controller firmware. */ static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws, - 0x744, BIT(0), 0); + 0x744, BIT(0), CLK_IS_CRITICAL); static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb0_hws, 0x784, BIT(0), 0);
base-commit: d89e1d186ec9271bf78e62771779e9fc03bf0fc3
prerequisite-patch-id: 0df2ae41836b86fd868dfa01ddfde57f888f761a
prerequisite-patch-id: 88f3a431e7c551a9fa732f062188f10fdd362eeb
prerequisite-patch-id: 3e88bc873c909059d1199f82cda4013765e7a5e5
prerequisite-patch-id: 0dbc27cd7417352319a0705a051dff35085e8922
prerequisite-patch-id: 0ed6b92774b5b794761c7ce34db653a5435dc833
prerequisite-patch-id: 27ed3814dbd0c7ad830532ff125625917c873b4b
prerequisite-patch-id: 74d03898c5ce14763f4e89fb73e021de59f0fb9f
prerequisite-patch-id: 9225cb094cf6cbb338b14ac63711d68bed12d24d
prerequisite-patch-id: 568dae1c91a0d7318d6eb14a18054343b84b603a
prerequisite-patch-id: ff3806332e741f0e2c8dac1c11f4c71449c16c8c
prerequisite-patch-id: 39461e0543aefb5c40184664625cbab19ac8408a
prerequisite-patch-id: 6fc03bfbd343042dd3b660938fcc09c5e7d48314
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2.53.0