Add support for MIPS P8700
Subsystems (5)
v2 cover Add support for MIPS P8700
The MIPS P8700 is a multi-core RISC-V microprocessor system, supporting both single-cluster and multi-cluster configurations. [1] This series adds full description of the platform,
including the Boston FPGA board configured with a P8700 bitfile.
The P8700 cores support the RV64GCZba_Zbb (G = IMAFD) Standard ISA, with a caveat: the A extension is only partially supported, and all ZAAMO extension instructions are emulated on the SBI level. The device tree intentionally does not reflect this fact. Vladimir Kondratiev's series improves performance by directly substituting AMO instructions with LR/SC. [4] The two patchsets do not depend on one another.
The board itself is the same board as 'img,boston', configured with a different bitfile [3]. The Boston board has been supported since commit 6e62a888029b ("MIPS: generic: Support MIPS Boston development boards") (thanks to Maciej for finding the ref).
GlobalFoundries has acquired MIPS [2] and the vendor prefix for all newly added MIPS RISC-V hardware reflects that fact.
I tested this series both on QEMU and a Boston board configured with a single P8700 CPU,
after applying the necessary U-Boot and OpenSBI changes
to match the 'compatible' strings and the changed MTIMER register order. We are planning to upstream these as well.
Links:
[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
[2] https://gf.com/news-and-events/news/globalfoundries-completes-acquisition-of-mips/
[3] https://training.mips.com/cps_mips/Examples/MD00901_Boot-MIPS_Example_Boot_Code_for_MIPS_Cores.pdf
[4] https://lore.kernel.org/all/[email protected]/
---
Changes in v2:
- Patch 1: Replace "MIPS Technology" with "MIPS Technologies".
- Patch 3: Name the FPGA used and add the versioned bitfile compatible.
- Patch 5: Drop hart indexes from MSWI.
- Patch 6: Swap mtimecmp and mtime, require reg-names both for mtime and mtimecmp on P8700.
- Original patch 7: Dropped.
- Patch 7 (previously 8): Remove additional harts that are not
present in the bitfile I have. Reflect changes made in patches 3, 5 and 6. Remove riscv,cbom-block-size. Drop undocumented compatibles. Other minor changes.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Aleksa Paunovic (8):
dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
dt-bindings: riscv: cpus: add gf,mips-p8700
dt-bindings: riscv: Add MIPS Boston board compatible
dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
riscv: dts: gf: Initial support for the P8700 Boston board
riscv: defconfig: Enable GF SoCs
.../bindings/interrupt-controller/riscv,aplic.yaml | 1 + .../thead,c900-aclint-mswi.yaml | 11 ++ Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + Documentation/devicetree/bindings/riscv/gf.yaml | 33 +++++ .../bindings/timer/thead,c900-aclint-mtimer.yaml | 35 ++++++ .../devicetree/bindings/vendor-prefixes.yaml | 4 +- arch/riscv/Kconfig.socs | 6 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/gf/Makefile | 2 + arch/riscv/boot/dts/gf/p8700-boston.dts | 135 +++++++++++++++++++++ arch/riscv/boot/dts/gf/p8700.dtsi | 82 +++++++++++++ arch/riscv/configs/defconfig | 1 + 12 files changed, 311 insertions(+), 1 deletion(-)
---
base-commit: fd73f4a6659897191fa0d40695fe370925dd3780
change-id: 20260325-p8700-dts-41788f014227
Best regards,
Signature · 1 line
Aleksa Paunovic <[email protected]>
PATCH v2 1/8 dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
GlobalFoundries acquired MIPS. All MIPS RISC-V compatibles should be labeled with the 'gf' prefix in the future.
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/vendor-prefixes.yaml +3 -1
@@ -668,6 +668,8 @@ patternProperties: description: Genexis BV/AB "^geniatech,.*": description: Geniatech, Inc. + "^gf,.*": + description: GlobalFoundries, Inc. "^giantec,.*": description: Giantec Semiconductor, Inc. "^giantplus,.*":
@@ -1104,7 +1106,7 @@ patternProperties: "^minix,.*": description: MINIX Technology Ltd. "^mips,.*": - description: MIPS Technology (deprecated, use 'mti' or 'img') + description: MIPS Technologies Inc. (deprecated, use 'mti', 'img', or 'gf') deprecated: true "^miramems,.*": description: MiraMEMS Sensing Technology Co., Ltd.
Signature · 1 line
2.43.0
PATCH v2 2/8 dt-bindings: riscv: cpus: add gf,mips-p8700
In reply to Aleksa PaunovicDocument the MIPS P8700 compatible.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -0
@@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - gf,mips-p8700 - nuclei,ux900 - sifive,bullet0 - sifive,e5
Signature · 1 line
2.43.0
Re: [PATCH v2 2/8] dt-bindings: riscv: cpus: add gf,mips-p8700
Quoted 3 lines · On Tue, Nov 03, 2026 at 04:11:26PM +0100, Aleksa Paunovic via B4 Relay wrote:
From: Aleksa Paunovic <[email protected]>
Document the MIPS P8700 compatible.
Same comment here.
pw-bot: not-applicable
Quoted 23 lines
Signed-off-by Aleksa Paunovic <[email protected]>--- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/riscv/cpus.yaml +1
-0@@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - gf,mips-p8700 - nuclei,ux900 - sifive,bullet0 - sifive,e5Signature · 2 lines
-- 2.43.0
PATCH v2 3/8 dt-bindings: riscv: Add MIPS Boston board compatible
In reply to Aleksa PaunovicDocument the MIPS Boston board compatible with a P8700 bitfile.
--- Documentation/devicetree/bindings/riscv/gf.yaml | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
Documentation/devicetree/bindings/riscv/gf.yaml new file +33 -0
@@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/gf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GlobalFoundries MIPS SoC-based boards + +maintainers: + - Djordje Todorovic <[email protected]> + - Aleksa Paunovic <[email protected]> + +description: + GlobalFoundries MIPS SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: | + Boston FPGA development board with a MIPS P8700 bitfile + + The Boston board carries a Xilinx XC7V2000T FPGA and fixed + peripherals: a Xilinx AXI PCIe root port, an Intel EG20T PCH, + a UART and an ASCII LCD. + items: + - const: gf,mips-p8700-boston-rtl-5057225-202410011144 + - const: gf,mips-p8700-boston + +additionalProperties: true + +...
Signature · 1 line
2.43.0
Re: [PATCH v2 3/8] dt-bindings: riscv: Add MIPS Boston board compatible
pw-bot: not-applicable
PATCH v2 4/8 dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
In reply to Aleksa PaunovicDocument the aplic compatible for the MIPS P8700.
--- Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +1 -0
@@ -27,6 +27,7 @@ properties: compatible: items: - enum: + - gf,mips-p8700-aplic - qemu,aplic - spacemit,k3-aplic - const: riscv,aplic
Signature · 1 line
2.43.0
Re: [PATCH v2 4/8] dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
Quoted 14 lines · On Tue, Nov 03, 2026 at 04:11:28PM +0100, Aleksa Paunovic via B4 Relay wrote:
From: Aleksa Paunovic <[email protected]>
Document the aplic compatible for the MIPS P8700.
Signed-off-by Aleksa Paunovic <[email protected]>--- Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +0
-0
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml properties: · line 30
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +1
-0@@ -27,6 +27,7 @@ properties: compatible: items: - enum: + - gf,mips-p8700-aplic
tbh, I don't like this because other devices on this "soc" are using mips,p8700-aplic and so I think this should be gf,p8700-aplic but I don't really care that much.
pw-bot: not-applicable
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +0
-0- qemu,aplic - spacemit,k3-aplic - const: riscv,aplicSignature · 2 lines
-- 2.43.0
PATCH v2 5/8 dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
In reply to Aleksa PaunovicDocument the aclint mswi compatible for the MIPS P8700.
--- .../bindings/interrupt-controller/thead,c900-aclint-mswi.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml +11 -0
@@ -21,6 +21,7 @@ properties: - enum: - anlogic,dr1v90-aclint-mswi - const: nuclei,ux900-aclint-mswi + - const: gf,mips-p8700-aclint-mswi reg: maxItems: 1
@@ -46,4 +47,14 @@ examples: <&cpu4intc 3>; reg = <0x94000000 0x00010000>; }; + + - | + mswi@16150000 { + compatible = "gf,mips-p8700-aclint-mswi"; + reg = <0x16150000 0x4000>; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + }; ...
Signature · 1 line
2.43.0
Re: [PATCH v2 5/8] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
Quoted 5 lines · On Tue, Nov 03, 2026 at 04:11:29PM +0100, Aleksa Paunovic via B4 Relay wrote:
From: Aleksa Paunovic <[email protected]>
Document the aclint mswi compatible for the MIPS P8700.
Signed-off-by Aleksa Paunovic <[email protected]>
Again, same comment :)
pw-bot: not-applicable
Quoted 41 lines
--- .../bindings/interrupt-controller/thead,c900-aclint-mswi.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml +11
-0@@ -21,6 +21,7 @@ properties: - enum: - anlogic,dr1v90-aclint-mswi - const: nuclei,ux900-aclint-mswi + - const: gf,mips-p8700-aclint-mswi reg: maxItems: 1@@ -46,4 +47,14 @@ examples: <&cpu4intc 3>; reg = <0x94000000 0x00010000>; }; + + - | + mswi@16150000 { + compatible = "gf,mips-p8700-aclint-mswi"; + reg = <0x16150000 0x4000>; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + };Signature · 9 lines
-- 2.43.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
PATCH v2 6/8 dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
In reply to Aleksa PaunovicDocument the MIPS P8700 ACLINT MTIMER. Extend support for both mtimecmp and mtime registers within the ACLINT MTIMER, identified via reg-names.
--- .../bindings/timer/thead,c900-aclint-mtimer.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+)
Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +35 -0
@@ -21,14 +21,19 @@ properties: - enum: - anlogic,dr1v90-aclint-mtimer - const: nuclei,ux900-aclint-mtimer + - const: gf,mips-p8700-aclint-mtimer reg: + minItems: 1 items: - description: MTIMECMP Registers + - description: MTIME Registers reg-names: + minItems: 1 items: - const: mtimecmp + - const: mtime interrupts-extended: minItems: 1
@@ -42,6 +47,25 @@ required: - reg-names - interrupts-extended +allOf: + - if: + properties: + compatible: + contains: + const: gf,mips-p8700-aclint-mtimer + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - | timer@ac000000 {
@@ -53,4 +77,15 @@ examples: reg = <0xac000000 0x00010000>; reg-names = "mtimecmp"; }; + + - | + timer@16154000 { + compatible = "gf,mips-p8700-aclint-mtimer"; + reg = <0x16154000 0x7ff8>, <0x16108050 0x8>; + reg-names = "mtimecmp", "mtime"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + }; ...
Signature · 1 line
2.43.0
Re: [PATCH v2 6/8] dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
Quoted 7 lines · On Tue, Nov 03, 2026 at 04:11:30PM +0100, Aleksa Paunovic via B4 Relay wrote:
From: Aleksa Paunovic <[email protected]>
Document the MIPS P8700 ACLINT MTIMER. Extend support for both mtimecmp and mtime registers within the ACLINT MTIMER, identified via reg-names.
Signed-off-by Aleksa Paunovic <[email protected]>
Same comments here too.
pw-bot: not-applicable
Quoted 75 lines
--- .../bindings/timer/thead,c900-aclint-mtimer.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+)Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +35
-0@@ -21,14 +21,19 @@ properties: - enum: - anlogic,dr1v90-aclint-mtimer - const: nuclei,ux900-aclint-mtimer + - const: gf,mips-p8700-aclint-mtimer reg: + minItems: 1 items: - description: MTIMECMP Registers + - description: MTIME Registers reg-names: + minItems: 1 items: - const: mtimecmp + - const: mtime interrupts-extended: minItems: 1@@ -42,6 +47,25 @@ required: - reg-names - interrupts-extended +allOf: + - if: + properties: + compatible: + contains: + const: gf,mips-p8700-aclint-mtimer + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - | timer@ac000000 {@@ -53,4 +77,15 @@ examples: reg = <0xac000000 0x00010000>; reg-names = "mtimecmp"; }; + + - | + timer@16154000 { + compatible = "gf,mips-p8700-aclint-mtimer"; + reg = <0x16154000 0x7ff8>, <0x16108050 0x8>; + reg-names = "mtimecmp", "mtime"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + };Signature · 2 lines
-- 2.43.0
Re: [PATCH v2 6/8] dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
Quoted 7 lines · Conor Dooley
Quoted 6 lines · On Tue, Nov 03, 2026 at 04:11:30PM +0100, Aleksa Paunovic via B4 Relay wrote:
From: Aleksa Paunovic <[email protected]>
Document the MIPS P8700 ACLINT MTIMER. Extend support for both mtimecmp and mtime registers within the ACLINT MTIMER, identified via reg-names.
Quoted 6 lines
Quoted 1 line
Signed-off-by Aleksa Paunovic <[email protected]>Same comments here too.
Acked-by Conor Dooley <[email protected]>pw-bot: not-applicable
On second thoughts, we probably need to be careful about the reg ordering here. This binding has always required that mtimecmp be "first" because it was the only let me rescind my ack for now and think about what the correct thing to do is...
Cheers,
Conor.
Quoted 76 lines
Quoted 76 lines
--- .../bindings/timer/thead,c900-aclint-mtimer.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+)Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +35
-0@@ -21,14 +21,19 @@ properties: - enum: - anlogic,dr1v90-aclint-mtimer - const: nuclei,ux900-aclint-mtimer + - const: gf,mips-p8700-aclint-mtimer reg: + minItems: 1 items: - description: MTIMECMP Registers + - description: MTIME Registers reg-names: + minItems: 1 items: - const: mtimecmp + - const: mtime interrupts-extended: minItems: 1@@ -42,6 +47,25 @@ required: - reg-names - interrupts-extended +allOf: + - if: + properties: + compatible: + contains: + const: gf,mips-p8700-aclint-mtimer + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - | timer@ac000000 {@@ -53,4 +77,15 @@ examples: reg = <0xac000000 0x00010000>; reg-names = "mtimecmp"; }; + + - | + timer@16154000 { + compatible = "gf,mips-p8700-aclint-mtimer"; + reg = <0x16154000 0x7ff8>, <0x16108050 0x8>; + reg-names = "mtimecmp", "mtime"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + };Signature · 2 lines
-- 2.43.0
PATCH v2 7/8 riscv: dts: gf: Initial support for the P8700 Boston board
In reply to Aleksa PaunovicAdd initial device tree for the MIPS P8700 and the device tree for the Boston FPGA development board with a MIPS P8700 bitfile.
Add related Makefile and KCONFIG changes.
--- arch/riscv/Kconfig.socs | 6 ++ arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/gf/Makefile | 2 + arch/riscv/boot/dts/gf/p8700-boston.dts | 135 ++++++++++++++++++++++++++++++++ arch/riscv/boot/dts/gf/p8700.dtsi | 82 +++++++++++++++++++ 5 files changed, 226 insertions(+)
arch/riscv/Kconfig.socs +6 -0
@@ -18,6 +18,12 @@ config ARCH_ESWIN This enables support for ESWIN SoC platform hardware, including the ESWIN EIC7700 SoC. +config ARCH_GF + bool "GlobalFoundries SoCs" + help + This enables support for GlobalFoundries SoC platform hardware, + including the MIPS P8700. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP
arch/riscv/boot/dts/Makefile +1 -0
@@ -4,6 +4,7 @@ subdir-y += andes subdir-y += anlogic subdir-y += canaan subdir-y += eswin +subdir-y += gf subdir-y += microchip subdir-y += renesas subdir-y += sifive
arch/riscv/boot/dts/gf/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_GF) += p8700-boston.dtb
arch/riscv/boot/dts/gf/p8700-boston.dts new file +135 -0
135 lines not on this page · raw message
arch/riscv/boot/dts/gf/p8700.dtsi new file +82 -0
82 lines not on this page · raw message
Signature · 1 line
2.43.0
Re: [PATCH v2 7/8] riscv: dts: gf: Initial support for the P8700 Boston board
arch/riscv/boot/dts/gf/p8700.dtsi line 74
Quoted 12 lines
arch/riscv/boot/dts/gf/p8700.dtsi new file +6
-0+ compatible = "gf,mips-p8700", "riscv"; + compatible = "gf,mips-p8700-aplic", "riscv,aplic"; + compatible = "gf,mips-p8700-aclint-mswi"; + compatible = "gf,mips-p8700-aclint-mtimer"; + compatible = "gf,mips-p8700-aplic", "riscv,aplic"; + compatible = "mips,p8700-aclint-sswi";
ngl, it'd look less stupid if you just called the whole thing mips,p8700-foo...
PATCH v2 8/8 riscv: defconfig: Enable GF SoCs
In reply to Aleksa PaunovicBuild the MIPS P8700 Boston dtb by default.
--- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +1 -0
@@ -25,6 +25,7 @@ CONFIG_PROFILING=y CONFIG_ARCH_ANDES=y CONFIG_ARCH_ANLOGIC=y CONFIG_ARCH_ESWIN=y +CONFIG_ARCH_GF=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y
Signature · 1 line
2.43.0
Re: [PATCH v2 8/8] riscv: defconfig: Enable GF SoCs
Quoted 55 lines · On Tue, Nov 03, 2026 at 04:11:24PM +0100, Aleksa Paunovic via B4 Relay wrote:
The MIPS P8700 is a multi-core RISC-V microprocessor system, supporting both single-cluster and multi-cluster configurations. [1] This series adds full description of the platform,
including the Boston FPGA board configured with a P8700 bitfile.The P8700 cores support the
RV64GCZba_Zbb(G = IMAFD) Standard ISA, with a caveat: the A extension is only partially supported, and all ZAAMO extension instructions are emulated on the SBI level. The device tree intentionally does not reflect this fact. Vladimir Kondratiev's series improves performance by directly substituting AMO instructions with LR/SC. [4] The two patchsets do not depend on one another.The board itself is the same board as 'img,boston', configured with a different bitfile [3]. The Boston board has been supported since commit
6e62a888029b("MIPS: generic: Support MIPS Boston development boards") (thanks to Maciej for finding the ref).GlobalFoundries has acquired MIPS [2] and the vendor prefix for all newly added MIPS RISC-V hardware reflects that fact.
I tested this series both on QEMU and a Boston board configured with a single P8700 CPU,
after applying the necessary U-Boot and OpenSBI changes
to match the 'compatible' strings and the changed MTIMER register order. We are planning to upstream these as well.Links:
[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
[2] https://gf.com/news-and-events/news/globalfoundries-completes-acquisition-of-mips/
[3] https://training.mips.com/cps_mips/Examples/MD00901_Boot-MIPS_Example_Boot_Code_for_MIPS_Cores.pdf
[4] https://lore.kernel.org/all/[email protected]/Signed-off-by Aleksa Paunovic <[email protected]>---
Changes in v2:
- Patch 1: Replace "MIPS Technology" with "MIPS Technologies".
- Patch 3: Name the FPGA used and add the versioned bitfile compatible.
- Patch 5: Drop hart indexes from MSWI.
- Patch 6: Swap mtimecmp and mtime, require reg-names both for mtime and mtimecmp on P8700.
- Original patch 7: Dropped.
- Patch 7 (previously 8): Remove additional harts that are not
present in the bitfile I have. Reflect changes made in patches 3, 5 and 6. Remove riscv,cbom-block-size. Drop undocumented compatibles. Other minor changes.
- Link to v1: https://lore.kernel.org/r/[email protected]---
Aleksa Paunovic (8):
dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
dt-bindings: riscv: cpus: add gf,mips-p8700
dt-bindings: riscv: Add MIPS Boston board compatible
dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
riscv: dts: gf: Initial support for the P8700 Boston board
riscv: defconfig: Enable GF SoCs
Quoted 13 lines
.../bindings/interrupt-controller/riscv,aplic.yaml | 1 + .../thead,c900-aclint-mswi.yaml | 11 ++ Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + Documentation/devicetree/bindings/riscv/gf.yaml | 33 +++++ .../bindings/timer/thead,c900-aclint-mtimer.yaml | 35 ++++++ .../devicetree/bindings/vendor-prefixes.yaml | 4 +- arch/riscv/Kconfig.socs | 6 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/gf/Makefile | 2 + arch/riscv/boot/dts/gf/p8700-boston.dts | 135 +++++++++++++++++++++ arch/riscv/boot/dts/gf/p8700.dtsi | 82 +++++++++++++ arch/riscv/configs/defconfig | 1 + 12 files changed, 311 insertions(+), 1 deletion(-)
You're missing a MAINTAINERS entry for the platform, since someone is going to have to pick up the patches for the arch/riscv/boot/dts/gf and that someone is neither Palmer nor Paul.
See Documentation/process/maintainer-soc.rst for more info.
I'd apply patches as a very last resort, but even then you'd need an entry to make sure that you're CCed on patches for the platform because I don't care about the platform and would just apply things that look correct if there was no reviews provided.
Cheers,
Conor.