phy: qcom-mipi-csi2: Add D-PHY support for sa8775p, qcs8300 and sc7280
v3 cover phy: qcom-mipi-csi2: Add D-PHY support for sa8775p, qcs8300 and sc7280
This series extends the generic Qualcomm MIPI CSI2 PHY driver (drivers/phy/qualcomm/phy-qcom-mipi-csi2-*) with three additional CSIPHY variants: SA8775P, QCS8300 and SC7280. The driver currently only supports x1e80100; these SoCs let CAMSS consume the CSIPHY through the common PHY framework instead of the CSIPHY logic embedded in the legacy in-tree CAMSS driver.
QCS8300 shares the same CSIPHY D-PHY hardware as SA8775P, so it does not need its own of_device_id entry: the qcom,csi2-phy.yaml binding declares "qcom,sa8775p-csi2-phy" as QCS8300's fallback compatible, and QCS8300 CSIPHY nodes bind through patch 3's existing "qcom,sa8775p-csi2-phy" match entry.
Tested on sa8775p, qcs8300 and sc7280.
Changes in v3:
- Patch 1 (binding): renamed vdda-phy-supply/vdda-pll-supply to vdda-hs-supply/vdda-lp-supply, and restored the DPHY split-mode port@0 definition (two endpoints, lane-count constraint) that was dropped from the combined schema, cloning it from qcom,x1e80100-csi2-phy.yaml instead.
- Dropped "phy: qcom-mipi-csi2: Make timer and OPP clock names configurable": no SoC this driver supports actually needs different clock names, so the patch had no real effect.
- Patch 2 ("Make OPP table optional") no longer depends on the dropped patch's configurable opp_clk_name field; it now adds a plain no_opp bool instead, with "timer"/"core" kept as hardcoded literals.
- Patches 3 and 4 (sa8775p, sc7280) dropped their now-unnecessary timer_clk_name/opp_clk_name overrides, and renamed their vdda-phy/vdda-pll supplies to vdda-hs/vdda-lp to match patch 1.
Link to v2: https://lore.kernel.org/all/[email protected]/
Changes in v2:
- Dropped "phy: qcom-mipi-csi2: fix -EEXIST probe failure on single power-domain SoCs" from this series; posted standalone instead, renamed to "Add support for single power-domain SoCs" since it adds a case rather than fixing a bug.
- Squashed the standalone qcom,sa8775p-csi2-phy.yaml/qcom,qcs8300 enum addition/qcom,sc7280-csi2-phy.yaml schemas into one shared qcom,csi2-phy.yaml, modelled as a oneOf compatible list instead of one file per SoC.
- Dropped the standalone "qcom,qcs8300-csi2-phy" of_device_id entry; QCS8300 now binds through the sa8775p match entry via the binding's fallback compatible instead, since the two SoCs are fully hardware compatible.
- Squashed the separate "Add qcs8300 CSI2 PHY support" patch into "Add sa8775p D-PHY support" to match.
Link to v1: https://lore.kernel.org/all/[email protected]/
Anusha Arun Nandi (4):
dt-bindings: phy: qcom: Add common qcom,csi2-phy
phy: qcom-mipi-csi2: Make OPP table optional
phy: qcom-mipi-csi2: Add sa8775p D-PHY support
phy: qcom-mipi-csi2: Add sc7280 D-PHY provider
.../bindings/phy/qcom,csi2-phy.yaml | 201 +++++++++++++++ .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 228 +++++++++++++++++- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 74 +++--- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 5 + 4 files changed, 474 insertions(+), 34 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
Best regards,
Signature · 4 lines
Anusha Arun Nandi <[email protected]> -- -- 2.34.1
PATCH v3 1/4 dt-bindings: phy: qcom: Add common qcom,csi2-phy
SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in devicetree shape (ports, bus-type, data-lanes, operating-points-v2, clocks, single "top" power-domain, vdda-hs/vdda-lp supplies).
Describe all three with a single qcom,csi2-phy.yaml and a compatible oneOf, rather than one standalone schema per SoC. QCS8300 is further required to be paired with a qcom,sa8775p-csi2-phy fallback compatible, the same way other Qualcomm bindings express full hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml); this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy match entry rather than carrying a duplicate one.
qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape (3 clocks, 3 power-domains, different supply names, DPHY split-mode support) and is left untouched, but port@0's DPHY split-mode definition (two endpoints, lane-count constraint) is cloned into this schema rather than dropped, since this PHY supports the same split mode.
The supply names are vdda-hs/vdda-lp rather than the hardware's own power-rail names, since those names aren't guaranteed to stay consistent across future platforms using this binding.
--- .../bindings/phy/qcom,csi2-phy.yaml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml new file +201 -0
@@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,csi2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CSI2 PHY + +maintainers: + - Anusha Arun Nandi <[email protected]> + +description: + Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera + CSI Decoder. + +properties: + compatible: + oneOf: + - enum: + - qcom,sa8775p-csi2-phy + - qcom,sc7280-csi2-phy + - items: + - enum: + - qcom,qcs8300-csi2-phy + - const: qcom,sa8775p-csi2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: timer + + interrupts: + maxItems: 1 + + operating-points-v2: true + + opp-table: + type: object + + power-domains: + items: + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + vdda-hs-supply: + description: Phandle to PHY supply. + + vdda-lp-supply: + description: Phandle to PLL supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Sensor input. Always present. A single sensor is described by a + single endpoint with one to four data lanes, numbered 1-4. The + clock lane is position 0. + + DPHY split mode, where two independent sensors share the PHY, is + described by two endpoints. endpoint@0 uses data lanes 1 or 1-2, + clock lane position 0; endpoint@1 uses data lane 3, clock lane + position 4. + + unevaluatedProperties: false + + patternProperties: + "^endpoint(@[01])?$": + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + default: 4 + + data-lanes: + minItems: 1 + maxItems: 4 + items: + minimum: 1 + maximum: 4 + description: + Data lane positions following this endpoint's clock + lane. Positions are a per-port logical numbering, not + package pad or ball positions. + + required: + - data-lanes + - remote-endpoint + + allOf: + - if: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + maxItems: 2 + items: + maximum: 2 + endpoint@1: + properties: + data-lanes: + items: + - const: 3 + required: + - endpoint@0 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the CAMSS CSID controller. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - operating-points-v2 + - power-domains + - power-domain-names + - vdda-hs-supply + - vdda-lp-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-camcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/media/video-interfaces.h> + + phy@ac9c000 { + compatible = "qcom,sa8775p-csi2-phy"; + reg = <0x0ac9c000 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + vdda-hs-supply = <&vreg_l4a>; + vdda-lp-supply = <&vreg_l1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy0_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; + }; + + port@1 { + reg = <1>; + csiphy0_out: endpoint { + remote-endpoint = <&csid_in>; + }; + }; + }; + + csiphy_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + };
Signature · 1 line
2.34.1
Re: [PATCH v3 1/4] dt-bindings: phy: qcom: Add common qcom,csi2-phy
Quoted 19 lines · Anusha Arun Nandi
SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in devicetree shape (ports, bus-type, data-lanes, operating-points-v2, clocks, single "top" power-domain, vdda-hs/vdda-lp supplies).
Describe all three with a single qcom,csi2-phy.yaml and a compatible oneOf, rather than one standalone schema per SoC. QCS8300 is further required to be paired with a qcom,sa8775p-csi2-phy fallback compatible, the same way other Qualcomm bindings express full hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml); this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy match entry rather than carrying a duplicate one.
qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape (3 clocks, 3 power-domains, different supply names, DPHY split-mode support) and is left untouched, but port@0's DPHY split-mode definition (two endpoints, lane-count constraint) is cloned into this schema rather than dropped, since this PHY supports the same split mode.
Quoted 5 lines
The supply names are vdda-hs/vdda-lp rather than the hardware's own power-rail names, since those names aren't guaranteed to stay consistent across future platforms using this binding.
Reviewed-by Jigarkumar Zala <[email protected]>
I do not see how you answered my questions.
Dropping from DT patchwork.
Best regards,
Krzysztof
PATCH v3 2/4 phy: qcom-mipi-csi2: Make OPP table optional
In reply to Anusha Arun NandiNot every SoC the generic MIPI CSI2 PHY driver supports needs an OPP
table: a CSIPHY with only a single, unscaled power-domain has no performance state to vote on, so running its "core" clock through the OPP framework buys nothing over a plain clk_set_rate(). Add a no_opp flag to struct mipi_csi2phy_soc_cfg and skip devm_pm_opp_set_clkname()/devm_pm_opp_of_add_table() in probe() and the OPP/performance-state handling in phy_qcom_mipi_csi2_set_clock_rates() when it's set, falling back to clk_round_rate()/clk_set_rate() on the timer clock only.
x1e80100 doesn't set no_opp, so this is a no-op for it. The "core"/ "timer" clock-name strings themselves stay hardcoded literals: every SoC this driver supports uses the same two names, so there's nothing to make configurable there.
--- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 72 ++++++++++--------- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 3 + 2 files changed, 42 insertions(+), 33 deletions(-)
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +39 -33
@@ -32,40 +32,43 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,unsigned long opp_rate = link_freq /4 ;struct dev_pm_opp *opp;long timer_rate; -int i, pstate; +int i =0 , pstate;int ret; - opp =dev_pm_opp_find_freq_ceil (dev, &opp_rate); -if (IS_ERR (opp)) { -dev_err (csi2phy->dev,"Couldn't find ceiling for %lld Hz\n" , - link_freq); -return PTR_ERR (opp); - } +if (!csi2phy->soc_cfg->no_opp) { + opp =dev_pm_opp_find_freq_ceil (dev, &opp_rate); +if (IS_ERR (opp)) { +dev_err (csi2phy->dev,"Couldn't find ceiling for %lld Hz\n" , + link_freq); +return PTR_ERR (opp); + } - pstate =0 ; -for (i =0 ; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) { -unsigned int perf; + pstate =0 ; +for (i =0 ; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) { +unsigned int perf; -if (!csi2phy->soc_cfg->genpds[i].scaled) -continue ; +if (!csi2phy->soc_cfg->genpds[i].scaled) +continue ; - perf =dev_pm_opp_get_required_pstate (opp, pstate); - pstate +=1 ; + perf =dev_pm_opp_get_required_pstate (opp, pstate); + pstate +=1 ; - ret =dev_pm_genpd_set_performance_state (csi2phy->pd_list->pd_devs[i], perf); -if (ret) { -dev_err (csi2phy->dev,"Couldn't set perf state %u\n" , - perf); -dev_pm_opp_put (opp); - goto unset_pstate; + ret =dev_pm_genpd_set_performance_state (csi2phy->pd_list->pd_devs[i], + perf); +if (ret) { +dev_err (csi2phy->dev,"Couldn't set perf state %u\n" , + perf); +dev_pm_opp_put (opp); + goto unset_pstate; + } } - } -dev_pm_opp_put (opp); +dev_pm_opp_put (opp); - ret =dev_pm_opp_set_rate (dev, opp_rate); -if (ret) { -dev_err (csi2phy->dev,"dev_pm_opp_set_rate() fail\n" ); - goto unset_opp_rate; + ret =dev_pm_opp_set_rate (dev, opp_rate); +if (ret) { +dev_err (csi2phy->dev,"dev_pm_opp_set_rate() fail\n" ); + goto unset_opp_rate; + } } timer_rate =clk_round_rate (csi2phy->timer_clk, link_freq /4 );
@@ -83,7 +86,8 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,return 0 ; unset_opp_rate: -dev_pm_opp_set_rate (dev,0 ); +if (!csi2phy->soc_cfg->no_opp) +dev_pm_opp_set_rate (dev,0 ); unset_pstate:while (i--) {
@@ -405,13 +409,15 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)if (!csi2phy->timer_clk)return dev_err_probe (dev, -ENODEV ,"no timer clock\n" ); - ret =devm_pm_opp_set_clkname (dev,"core" ); -if (ret) -return dev_err_probe (dev, ret,"Failed to set opp clkname\n" ); +if (!csi2phy->soc_cfg->no_opp) { + ret =devm_pm_opp_set_clkname (dev,"core" ); +if (ret) +return dev_err_probe (dev, ret,"Failed to set opp clkname\n" ); - ret =devm_pm_opp_of_add_table (dev); -if (ret) -return dev_err_probe (dev, ret,"invalid OPP table in device tree\n" ); + ret =devm_pm_opp_of_add_table (dev); +if (ret) +return dev_err_probe (dev, ret,"invalid OPP table in device tree\n" ); + } num_supplies = csi2phy->soc_cfg->num_supplies; csi2phy->supplies = devm_kzalloc(dev, sizeof(*csi2phy->supplies) * num_supplies,
drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +3 -0
@@ -68,6 +68,9 @@ struct mipi_csi2phy_soc_cfg {const char **const clk_names;const unsigned int num_clk; +/* Skip OPP-based clock/pstate scaling. */ +const bool no_opp; +const struct mipi_csi2_genpd *genpds;const unsigned int num_genpds; };
Signature · 1 line
2.34.1
PATCH v3 3/4 phy: qcom-mipi-csi2: Add sa8775p D-PHY support
In reply to Anusha Arun NandiAdd the SA8775P CSIPHY to the generic MIPI CSI2 PHY driver, bound to a new "qcom,sa8775p-csi2-phy" compatible
and reusing the existing D-PHY 2-phase hw ops (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sa8775p[] init sequence is the CSIPHY v1.3.0 2-phase 2.5Gbps 4-lane D-PHY register set ported verbatim from the legacy in-tree camss-csiphy-3ph-1-0.c table; common_regs_offset is 0x800.
SA8775P reuses the same "timer"/"core" clock names as x1e80100 (both are hardcoded literals in the driver, not per-SoC configurable - no SoC this driver supports uses different names). Like x1e80100, its CSIPHY core clock is OPP-scaled against the sensor's link frequency via the shared csiphy_opp_table in lemans.dtsi, matching the legacy in-tree CSIPHY driver's own sa8775p_resources OPP wiring.
SA8775P's CSIPHY has a single power-domain, the Titan Top GDSC, matching the legacy in-tree CAMSS driver's sa8775p_resources.pd_name = "top" and the existing lemans.dtsi camss node. Like x1e80100's own "top" domain, it is not OPP-scaled, only kept enabled.
QCS8300 shares this same CSIPHY D-PHY hardware and does not need its own of_device_id entry: the qcom,csi2-phy.yaml binding declares "qcom,sa8775p-csi2-phy" as QCS8300's fallback compatible, so QCS8300 CSIPHY nodes bind through the "qcom,sa8775p-csi2-phy" match entry added here.
--- .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 108 +++++++++++++++++- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 3 files changed, 109 insertions(+), 1 deletion(-)
drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +107 -1
@@ -317,7 +317,6 @@ static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy,writel (val, csi2phy->base +CSIPHY_3PH_CMN_CSI_COMMON_CTRLn (regs->common_regs_offset,7 )); - val =0x00 ;writel (val, csi2phy->base +CSIPHY_3PH_CMN_CSI_COMMON_CTRLn (regs->common_regs_offset,0 ));
@@ -383,3 +382,110 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .genpds = x1e_genpds, .num_genpds = ARRAY_SIZE(x1e_genpds), }; + +/* 5nm 2PH v1.3.0 2p5Gbps 4 lane DPHY mode */ +static const struct mipi_csi2phy_lane_regs lane_regs_sa8775p[] = { + {.reg_addr =0x0724 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0728 , .reg_data =0x04 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0700 , .reg_data =0x80 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x070c , .reg_data =0xff , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0738 , .reg_data =0x1f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x072c , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0734 , .reg_data =0x0f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0710 , .reg_data =0x52 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x071c , .reg_data =0x0a , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0714 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x073c , .reg_data =0xb8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0704 , .reg_data =0x0c , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0720 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0708 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0024 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0000 , .reg_data =0x8d , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0038 , .reg_data =0xfe , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x002c , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0034 , .reg_data =0x0f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0010 , .reg_data =0x52 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x001c , .reg_data =0x0a , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0014 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x003c , .reg_data =0xb8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0004 , .reg_data =0x0c , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0020 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0008 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0224 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0200 , .reg_data =0x8d , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0238 , .reg_data =0xfe , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x022c , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0234 , .reg_data =0x0f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0210 , .reg_data =0x52 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x021c , .reg_data =0x0a , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0214 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x023c , .reg_data =0xb8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0204 , .reg_data =0x0c , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0220 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0208 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0424 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0400 , .reg_data =0x8d , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0438 , .reg_data =0xfe , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x042c , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0434 , .reg_data =0x0f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0410 , .reg_data =0x52 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x041c , .reg_data =0x0a , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0414 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x043c , .reg_data =0xb8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0404 , .reg_data =0x0c , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0420 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0408 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0624 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0600 , .reg_data =0x8d , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0638 , .reg_data =0xfe , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x062c , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0634 , .reg_data =0x0f , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0610 , .reg_data =0x52 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x061c , .reg_data =0x0a , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0614 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x063c , .reg_data =0xb8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0604 , .reg_data =0x0c , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0620 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0608 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x005c , .reg_data =0x00 , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0060 , .reg_data =0xfd , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0064 , .reg_data =0x7f , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x025c , .reg_data =0x00 , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0260 , .reg_data =0xfd , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0264 , .reg_data =0x7f , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x045c , .reg_data =0x00 , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0460 , .reg_data =0xfd , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0464 , .reg_data =0x7f , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x065c , .reg_data =0x00 , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0660 , .reg_data =0xfd , .param_type =CSIPHY_SKEW_CAL }, + {.reg_addr =0x0664 , .reg_data =0x7f , .param_type =CSIPHY_SKEW_CAL }, +}; + +static const char *const sa8775p_clks[] = { +"core" , +"timer" , +}; + +static const char *const sa8775p_supplies[] = { +"vdda-hs" , +"vdda-lp" , +}; + +static const struct mipi_csi2_genpd sa8775p_genpds[] = { + { .name ="top" , .scaled = false }, +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_sa8775p, + .lane_array_size =ARRAY_SIZE (lane_regs_sa8775p), + .common_regs_offset =0x800 , + }, + .supply_names = (const char **)sa8775p_supplies, + .num_supplies =ARRAY_SIZE (sa8775p_supplies), + .clk_names = (const char **)sa8775p_clks, + .num_clk =ARRAY_SIZE (sa8775p_clks), + .genpds = sa8775p_genpds, + .num_genpds =ARRAY_SIZE (sa8775p_genpds), +};
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +1 -0
@@ -454,6 +454,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) }static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { + { .compatible ="qcom,sa8775p-csi2-phy" , .data = &mipi_csi2_dphy_sa8775p }, { .compatible ="qcom,x1e80100-csi2-phy" , .data = &mipi_csi2_dphy_4nm_x1e }, { } };
drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +1 -0
@@ -96,5 +96,6 @@ struct mipi_csi2phy_device { };extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p;#endif /* __PHY_QCOM_MIPI_CSI2_H__ */
Signature · 1 line
2.34.1
PATCH v3 4/4 phy: qcom-mipi-csi2: Add sc7280 D-PHY provider
In reply to Anusha Arun NandiAdd the SC7280 CSIPHY to the generic MIPI CSI2 PHY driver, bound to a new "qcom,sc7280-csi2-phy" compatible
and reusing the existing D-PHY 2-phase hw ops (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sc7280[] init sequence is the CSIPHY 5nm 2-phase 2.5Gbps 4-lane D-PHY register set ported from the legacy in-tree camss-csiphy-3ph-1-0.c table, with the entries that table left as do-not-program placeholders simply omitted here rather than carried as a new marker. The soc_cfg declares the core/timer clocks (matching x1e80100's and sa8775p's clock-names convention for this pair, both hardcoded literals in the driver) and the vdda-hs/vdda-lp supplies.
Like x1e80100 and SA8775P, SC7280's CSIPHY core clock is OPP-scaled against the sensor's link frequency via the shared csiphy_opp_table in kodiak.dtsi, so no_opp is left unset here too. SC7280's CSIPHY has a single power-domain, the Titan Top GDSC, matching camss.c's sc7280_resources.pd_name = "top" and kodiak.dtsi's existing camss node; it is not OPP-scaled, only kept enabled.
--- .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 120 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 3 files changed, 122 insertions(+)
drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +120 -0
@@ -489,3 +489,123 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p = { .genpds = sa8775p_genpds, .num_genpds = ARRAY_SIZE(sa8775p_genpds), }; + +/* sc7280 5nm 2PH 2p5Gbps 4 lane DPHY mode */ +static const struct mipi_csi2phy_lane_regs lane_regs_sc7280[] = { + {.reg_addr =0x0030 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0900 , .reg_data =0x05 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0908 , .reg_data =0x10 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0904 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0904 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0004 , .reg_data =0x0C , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x002C , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0034 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0010 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x001C , .reg_data =0x08 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x003C , .reg_data =0xB8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0008 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0000 , .reg_data =0x8D , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0038 , .reg_data =0xFE , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0014 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0800 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0884 , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0730 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C80 , .reg_data =0x05 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C88 , .reg_data =0x10 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C84 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C84 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0704 , .reg_data =0x0C , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x072C , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0734 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0710 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x071C , .reg_data =0x08 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x073C , .reg_data =0xB8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0708 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0700 , .reg_data =0x80 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x070c , .reg_data =0xA5 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0738 , .reg_data =0x1F , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0714 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0728 , .reg_data =0x04 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0800 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0884 , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0230 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0A00 , .reg_data =0x05 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0A08 , .reg_data =0x10 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0A04 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0A04 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0204 , .reg_data =0x0C , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x022C , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0234 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0210 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x021C , .reg_data =0x08 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x023C , .reg_data =0xB8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0208 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0200 , .reg_data =0x8D , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0238 , .reg_data =0xFE , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0214 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0800 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0884 , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0430 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0B00 , .reg_data =0x05 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0B08 , .reg_data =0x10 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0B04 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0B04 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0404 , .reg_data =0x0C , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x042C , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0434 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0410 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x041C , .reg_data =0x08 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x043C , .reg_data =0xB8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0408 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0400 , .reg_data =0x8D , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0438 , .reg_data =0xFE , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0414 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0800 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0884 , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0630 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C00 , .reg_data =0x05 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C08 , .reg_data =0x10 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C04 , .reg_data =0x00 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0C04 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0604 , .reg_data =0x0C , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x062C , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0634 , .reg_data =0x07 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0610 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x061C , .reg_data =0x08 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x063C , .reg_data =0xB8 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0608 , .reg_data =0x10 , .param_type =CSIPHY_SETTLE_CNT_LOWER_BYTE }, + {.reg_addr =0x0600 , .reg_data =0x8D , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0638 , .reg_data =0xFE , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0614 , .reg_data =0x60 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0800 , .reg_data =0x02 , .param_type =CSIPHY_DEFAULT_PARAMS }, + {.reg_addr =0x0884 , .reg_data =0x01 , .param_type =CSIPHY_DEFAULT_PARAMS }, +}; + +static const char *const sc7280_clks[] = { +"core" , +"timer" , +}; + +static const char *const sc7280_supplies[] = { +"vdda-hs" , +"vdda-lp" , +}; + +static const struct mipi_csi2_genpd sc7280_genpds[] = { + { .name ="top" , .scaled = false }, +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280 = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_sc7280, + .lane_array_size =ARRAY_SIZE (lane_regs_sc7280), + .common_regs_offset =0x800 , + }, + .supply_names = (const char **)sc7280_supplies, + .num_supplies =ARRAY_SIZE (sc7280_supplies), + .clk_names = (const char **)sc7280_clks, + .num_clk =ARRAY_SIZE (sc7280_clks), + .genpds = sc7280_genpds, + .num_genpds =ARRAY_SIZE (sc7280_genpds), +};
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +1 -0
@@ -455,6 +455,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { { .compatible ="qcom,sa8775p-csi2-phy" , .data = &mipi_csi2_dphy_sa8775p }, + { .compatible ="qcom,sc7280-csi2-phy" , .data = &mipi_csi2_dphy_sc7280 }, { .compatible ="qcom,x1e80100-csi2-phy" , .data = &mipi_csi2_dphy_4nm_x1e }, { } };
drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +1 -0
@@ -97,5 +97,6 @@ struct mipi_csi2phy_device {extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e;extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p; +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280;#endif /* __PHY_QCOM_MIPI_CSI2_H__ */
Signature · 1 line
2.34.1
Hi Krzysztof,
Sorry for missing the answers in v2. Here are the answers to questions in v2.
1. Q:
https://lore.kernel.org/all/[email protected]/#t
v1 link is -
https://lore.kernel.org/all/[email protected]/
v2 link is -
https://lore.kernel.org/all/[email protected]/
In this v3. these comments have been addressed and updated
accordingly.
2. Q:
https://lore.kernel.org/all/[email protected]/
That Reviewed-by was given in an internal review, not on a public
list thread.
3. Q:
https://lore.kernel.org/all/[email protected]/
Agreed on both points. Why it existed: it wasn't added on a guess
that some SoCs would need a different names. In v1
(https://lore.kernel.org/all/[email protected]/),
timer_clk_name/opp_clk_name were added inline as part of the sa8775p patch itself. Bryan asked only that it be split into its own standalone patch ahead of the SoC work(https://lore.kernel.org/all/[email protected]/), not that the configurability be justified or kept. I did the split for v2 to verify whether the original premise still made sense. This driver does not support platforms such as x1e80100, sa8775p, or sc7280, nor do any of them ever declare a different clock name.
Dropping the patch entirely in v3 rather than reworking it.
"timer"/"core" go back to being hardcoded literals, same as before v1 introduced the configurable fields.
4. Q:
https://lore.kernel.org/all/[email protected]/
Reviewed-by: given in an internal review, not on a public thread, no
lore link exists.
On sc7280_clks[] and "what is the point of patch #2", the array
itself has a point: each SoC's soc_cfg needs its own two-entry clk_names array matching its DT clock-names, same as x1e80100's and sa8775p's. What had no point was patch #2 (dropped in v3) adding a second, overridable name on top of that array, timer_clk_name/opp_clk_name, when every one of those arrays already says, "core"/"timer" and nothing ever varies it. In v3, sc7280_clks[] = {"core", "timer"} stands on its own, unconditionally used, no override field anywhere.
Best regards,
Anusha
Quoted 66 lines · Anusha Arun Nandi
This series extends the generic Qualcomm MIPI CSI2 PHY driver (
drivers/phy/qualcomm/phy-qcom-mipi-csi2-*) with three additional CSIPHY variants: SA8775P, QCS8300 and SC7280. The driver currently only supports x1e80100; these SoCs let CAMSS consume the CSIPHY through the common PHY framework instead of the CSIPHY logic embedded in the legacy in-tree CAMSS driver.QCS8300 shares the same CSIPHY D-PHY hardware as SA8775P, so it does not need its own
of_device_identry: the qcom,csi2-phy.yaml binding declares "qcom,sa8775p-csi2-phy" as QCS8300's fallback compatible, and QCS8300 CSIPHY nodes bind through patch 3's existing "qcom,sa8775p-csi2-phy" match entry.Tested on sa8775p, qcs8300 and sc7280.
Changes in v3:
- Patch 1 (binding): renamed vdda-phy-supply/vdda-pll-supply to vdda-hs-supply/vdda-lp-supply, and restored the DPHY split-mode port@0 definition (two endpoints, lane-count constraint) that was dropped from the combined schema, cloning it from qcom,x1e80100-csi2-phy.yaml instead.
- Dropped "phy: qcom-mipi-csi2: Make timer and OPP clock names configurable": no SoC this driver supports actually needs different clock names, so the patch had no real effect.
- Patch 2 ("Make OPP table optional") no longer depends on the dropped patch's configurableopp_clk_namefield; it now adds a plainno_oppbool instead, with "timer"/"core" kept as hardcoded literals.
- Patches 3 and 4 (sa8775p, sc7280) dropped their now-unnecessary timer_clk_name/opp_clk_name overrides, and renamed their vdda-phy/vdda-pll supplies to vdda-hs/vdda-lp to match patch 1.Link to v2: https://lore.kernel.org/all/[email protected]/
Changes in v2:
- Dropped "phy: qcom-mipi-csi2: fix-EEXISTprobe failure on single power-domain SoCs" from this series; posted standalone instead, renamed to "Add support for single power-domain SoCs" since it adds a case rather than fixing a bug.
- Squashed the standalone qcom,sa8775p-csi2-phy.yaml/qcom,qcs8300 enumaddition/qcom,sc7280-csi2-phy.yamlschemas into one shared qcom,csi2-phy.yaml, modelled as a oneOf compatible list instead of one file per SoC.
- Dropped the standalone "qcom,qcs8300-csi2-phy"of_device_identry; QCS8300 now binds through the sa8775p match entry via the binding's fallback compatible instead, since the two SoCs are fully hardware compatible.
- Squashed the separate "Add qcs8300 CSI2 PHY support" patch into "Add sa8775p D-PHY support" to match.Link to v1: https://lore.kernel.org/all/[email protected]/
Anusha Arun Nandi (4):
dt-bindings: phy: qcom: Add common qcom,csi2-phy
phy: qcom-mipi-csi2: Make OPP table optional
phy: qcom-mipi-csi2: Add sa8775p D-PHY support
phy: qcom-mipi-csi2: Add sc7280 D-PHY provider.../bindings/phy/qcom,csi2-phy.yaml | 201 +++++++++++++++ .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 228 +++++++++++++++++- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 74 +++--- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 5 + 4 files changed, 474 insertions(+), 34 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yamlBest regards,