media: qcom: camss: Add SM8150 CAMSS support

From: Andrew Gigena <[email protected]>

Add qcom,sm8150-cci as a CCI v2 compatible, with qcom,msm8996-cci as the fallback.

Signed-off-by Andrew Gigena <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
  Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
  1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +1 -0

index 1e8def25ec0e..1e7a8efaa398 100644
@@ -39,6 +39,7 @@ properties:
                - qcom,shikra-cci
                - qcom,sm6150-cci
                - qcom,sm6350-cci
+              - qcom,sm8150-cci
                - qcom,sm8250-cci
                - qcom,sm8450-cci
                - qcom,sm8550-cci

From: Andrew Gigena <[email protected]>

Add qcom,sm8150-cci as a CCI v2 compatible, with qcom,msm8996-cci as the fallback.

Signed-off-by Andrew Gigena <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Reviewed-by Vladimir Zapolskiy <[email protected]>

From: Andrew Gigena <[email protected]>

Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite instances, with 19 clocks, 8 interrupts, eight IOMMU streams, four interconnect paths and three power domains.

The CSIPHY I/O spaces are not part of the CAMSS container device: each CSIPHY is driven by the dedicated qcom,sm8150-csi2-phy driver, so this binding only describes the VFE and CSID resources. Each CSI input port is described with data lanes starting at 1, as required by the CAMSS PHY mode.

Describe SM8150 in a dedicated schema instead of reusing another SoC's schema.

Signed-off-by Andrew Gigena <[email protected]>

---
  .../bindings/media/qcom,sm8150-camss.yaml          | 285 +++++++++++++++++++++
  1 file changed, 285 insertions(+)

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +21 -0

new file mode 100644
index 000000000000..371ff1ce0bd2
@@ -0,0 +1,285 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 Camera Subsystem (CAMSS)
+
+maintainers:
+  - Andrew Gigena <[email protected]>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,sm8150-camss
+
+  reg:
+    maxItems: 8
+

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +15 -0

+
+  clocks:
+    maxItems: 19
+
+  clock-names:
+    items:
+      - const: camnoc_axi
+      - const: cpas_ahb
+      - const: vfe0_axi
+      - const: vfe0
+      - const: vfe0_cphy_rx
+      - const: vfe0_csid
+      - const: vfe1_axi
+      - const: vfe1
+      - const: vfe1_cphy_rx

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +4 -0

+
+  interrupts:
+    maxItems: 8
+

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +36 -0

+
+  iommus:
+    maxItems: 8
+
+  power-domains:
+    items:
+      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+  power-domain-names:
+    items:
+      - const: ife0
+      - const: ife1
+      - const: top
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    description:
+      CSI input ports, one per CSI2 PHY instance.
+
+    patternProperties:
+      "^port@[0-3]$":
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+
+        description:
+          Input port for receiving CSI data from a CSIPHY.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +159 -0

+
+            required:
+              - data-lanes
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interconnects
+  - interconnect-names
+  - interrupts
+  - interrupt-names
+  - iommus
+  - power-domains
+  - power-domain-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+    #include <dt-bindings/clock/qcom,sm8150-camcc.h>
+    #include <dt-bindings/interconnect/qcom,sm8150.h>
+    #include <dt-bindings/media/video-interfaces.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        isp@acaf000 {
+            compatible = "qcom,sm8150-camss";
+
+            reg = <0 0xacaf000 0 0x4000>,
+                  <0 0xacb3000 0 0x1000>,
+                  <0 0xacb6000 0 0x4000>,
+                  <0 0xacba000 0 0x1000>,
+                  <0 0xacc4000 0 0x4000>,
+                  <0 0xacc8000 0 0x1000>,
+                  <0 0xaccb000 0 0x4000>,
+                  <0 0xaccf000 0 0x1000>;
+
+            reg-names = "vfe0",
+                        "csid0",
+                        "vfe1",
+                        "csid1",
+                        "vfe_lite0",
+                        "csid_lite0",
+                        "vfe_lite1",
+                        "csid_lite1";
+
+            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                     <&camcc CAM_CC_CPAS_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_0_CLK>,
+                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_1_CLK>,
+                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
+                     <&gcc GCC_CAMERA_AHB_CLK>,
+                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                     <&gcc GCC_CAMERA_SF_AXI_CLK>;
+
+            clock-names = "camnoc_axi",
+                          "cpas_ahb",
+                          "vfe0_axi",
+                          "vfe0",
+                          "vfe0_cphy_rx",
+                          "vfe0_csid",
+                          "vfe1_axi",
+                          "vfe1",
+                          "vfe1_cphy_rx",
+                          "vfe1_csid",
+                          "vfe_lite0",
+                          "vfe_lite0_cphy_rx",
+                          "vfe_lite0_csid",
+                          "vfe_lite1",
+                          "vfe_lite1_cphy_rx",
+                          "vfe_lite1_csid",
+                          "gcc_ahb",
+                          "gcc_axi_hf",
+                          "gcc_axi_sf";
+
+            interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
+
+            interrupt-names = "vfe0",
+                              "csid0",
+                              "vfe1",
+                              "csid1",
+                              "vfe_lite0",
+                              "csid_lite0",
+                              "vfe_lite1",
+                              "csid_lite1";
+
+            power-domains = <&camcc IFE_0_GDSC>,
+                            <&camcc IFE_1_GDSC>,
+                            <&camcc TITAN_TOP_GDSC>;
+
+            power-domain-names = "ife0",
+                                 "ife1",
+                                 "top";
+
+            interconnects = <&gem_noc MASTER_AMPSS_M0 0
+                             &config_noc SLAVE_CAMERA_CFG 0>,
+                            <&mmss_noc MASTER_CAMNOC_HF0 0
+                             &mc_virt SLAVE_EBI_CH0 0>,
+                            <&mmss_noc MASTER_CAMNOC_SF 0
+                             &mc_virt SLAVE_EBI_CH0 0>,
+                            <&mmss_noc MASTER_CAMNOC_HF1 0
+                             &mc_virt SLAVE_EBI_CH0 0>;
+
+            interconnect-names = "cam_ahb",
+                                 "cam_hf_0_mnoc",
+                                 "cam_sf_0_mnoc",
+                                 "cam_hf_1_mnoc";
+
+            iommus = <&apps_smmu 0x840 0x620>,
+                     <&apps_smmu 0x860 0x620>,
+                     <&apps_smmu 0xa40 0x620>,
+                     <&apps_smmu 0xa60 0x620>,
+                     <&apps_smmu 0xc40 0x620>,
+                     <&apps_smmu 0xc60 0x620>,
+                     <&apps_smmu 0xe40 0x620>,
+                     <&apps_smmu 0xe60 0x620>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    endpoint {
+                        bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                        data-lanes = <1 2 3 4>;
+                        remote-endpoint = <&csiphy0_out>;
+                    };
+                };
+            };
+        };
+    };

That's an intermix of names, and you will get a review comment from Krzysztof about it, I stand aside.

Here too.

Drop 'gcc_axi_sf'.

Drop 'cam_' prefix and 'cam_sf_0_mnoc' also.

Or C-PHY, right?..
In fact you shall drop bus-type from here, because the link between CAMSS and PHY's output is not a CSI-2 bus, it makes it inapplicable.

Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite instances, with 19 clocks, 8 interrupts, eight IOMMU streams, four interconnect paths and three power domains.

The CSIPHY I/O spaces are not part of the CAMSS container device: each CSIPHY is driven by the dedicated qcom,sm8150-csi2-phy driver, so this binding only describes the VFE and CSID resources. Each CSI input port is described with data lanes starting at 1, as required by the CAMSS PHY mode.

Describe SM8150 in a dedicated schema instead of reusing another SoC's schema.

Signed-off-by Andrew Gigena <[email protected]>

---
 .../bindings/media/qcom,sm8150-camss.yaml          | 285 +++++++++++++++++++++
 1 file changed, 285 insertions(+)

Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml new file +21 -0

new file mode 100644
index 000000000000..371ff1ce0bd2
@@ -0,0 +1,285 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 Camera Subsystem (CAMSS)
+
+maintainers:
+  - Andrew Gigena <[email protected]>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,sm8150-camss
+
+  reg:
+    maxItems: 8
+

From: Andrew Gigena <[email protected]>

Document the Qualcomm SM8150 MIPI CSI2 D-PHY. The PHY sits between the CSI2 sensor and the CAMSS CSI decoder and is fed by the CSIPHY "core" and "timer" clocks, the TITAN top power domain and the vdda-phy/vdda-pll supplies.

Unlike the X1E80100 C-PHY/D-PHY combo PHY, SM8150 only has a D-PHY, has no separate AHB clock and no MMCX/MX power domains, so describe it in a dedicated schema.

Signed-off-by Andrew Gigena <[email protected]>

---
  .../bindings/phy/qcom,sm8150-csi2-phy.yaml         | 163 +++++++++++++++++++++
  1 file changed, 163 insertions(+)

Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml new file +34 -0

new file mode 100644
index 000000000000..86d8970d1119
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,sm8150-csi2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 SoC CSI2 PHY
+
+maintainers:
+  - Andrew Gigena <[email protected]>
+
+description:
+  Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera
+  CSI decoder (CAMSS).
+
+properties:
+  compatible:
+    const: qcom,sm8150-csi2-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: core
+      - const: timer
+
+  interrupts:
+    maxItems: 1
+
+  operating-points-v2: true

Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml new file +4 -0

+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+

Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml new file +81 -0

+
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+                items:
+                  minimum: 1
+                  maximum: 4
+
+            required:
+              - data-lanes
+              - remote-endpoint
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output to the CAMSS CSI input port.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - operating-points-v2
+  - power-domains
+  - power-domain-names
+  - vdda-phy-supply
+  - vdda-pll-supply
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,sm8150-camcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/media/video-interfaces.h>
+
+    phy@ac65000 {
+        compatible = "qcom,sm8150-csi2-phy";
+        reg = <0xac65000 0x1000>;
+
+        clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
+        clock-names = "core",
+                      "timer";
+
+        interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+        operating-points-v2 = <&csiphy0_opp_table>;
+
+        power-domains = <&camcc TITAN_TOP_GDSC>;
+        power-domain-names = "top";
+
+        vdda-phy-supply = <&vreg_l5a_0p88>;
+        vdda-pll-supply = <&vreg_l12a_1p2>;
+
+        csiphy0_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-400000000 {
+                opp-hz = /bits/ 64 <400000000>;
+            };
+        };
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                endpoint {
+                    bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                    data-lanes = <1 2 3 4>;
+                    remote-endpoint = <&sensor_out>;
+                };
+            };

Please double check if SM8150 CSIPHY v1.1 is capable of C-PHY:

D-PHY combo mode is also supported on the SM8150 CSIPHY apparently, it shall be reflected in a way that two endpoints could be present.

In downstream camcc-sm8150.c, PLL0 is on MX, and PLL0 supplies CSIPHY clocks. I believe MX shall be added to the list of 'power-domains'.

Still it would be preferred to get 'vdda-0p9-supply' and 'vdda-1p2-supply' properties.

In general the change looks good, thank you, but likely it can be embedded into the scheme for X1E.

Documentation/devicetree/bindings/phy/qcom,sm8150-csi2-phy.yaml new file +26 -0

+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Sensor input. A single sensor is described by a single endpoint with
+          one to four data lanes, numbered 1-4. The clock lane is position 0.
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              bus-type:
+                enum:
+                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+                default: 4
+
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+                items:

drivers/media/platform/qcom/camss/camss-vfe.c +4 -0

@@ -346,6 +347,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
  	case CAMSS_6350:
  	case CAMSS_7280:
  	case CAMSS_8x96:
+	case CAMSS_8150:
  	case CAMSS_8250:
  	case CAMSS_8280XP:
  	case CAMSS_8300:

@@ -914,6 +916,9 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
  	return (!strcmp(clock->name, vfe_name) ||
  		!strcmp(clock->name, vfe_lite_name) ||
  		!strcmp(clock->name, "vfe_lite") ||
+		(vfe->res->is_lite &&
+		 !strncmp(clock->name, "vfe_lite", 8) &&
+		 isdigit((unsigned char)clock->name[8])) ||
  		!strcmp(clock->name, "camnoc_axi") ||
  		!strcmp(clock->name, "camnoc_rt_axi"));
  }

From: Andrew Gigena <[email protected]>

Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera subsystem contains four CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite instances.

The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and VFE 17x implementations; the CSIPHY uses the SC8280XP lane register layout. Add CAMSS_8150 to the version enum and to the shared code paths, then add the per-block clock, regulator, power domain, interrupt and interconnect resources.

The CSIPHY resources are reduced to id/hw_ops/formats only; clocks, regulators, registers and interrupts are owned by the dedicated CSI2 PHY driver.

Signed-off-by Andrew Gigena <[email protected]>

---
  .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     |   2 +
  drivers/media/platform/qcom/camss/camss.c          | 231 +++++++++++++++++++++
  drivers/media/platform/qcom/camss/camss.h          |   1 +
  3 files changed, 234 insertions(+)

drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +2 -0

index dac8d2ecf799..5e7c2e67ae88 100644
@@ -1133,6 +1133,7 @@ static bool csiphy_is_gen2(u32 version)
  	case CAMSS_6150:
  	case CAMSS_6350:
  	case CAMSS_7280:
+	case CAMSS_8150:
  	case CAMSS_8250:
  	case CAMSS_8280XP:
  	case CAMSS_8300:

@@ -1235,6 +1236,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
  		regs->lane_regs = &lane_regs_sm8250[0];
  		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
  		break;
+	case CAMSS_8150:
  	case CAMSS_8280XP:
  		regs->lane_regs = &lane_regs_sc8280xp[0];
  		regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);

drivers/media/platform/qcom/camss/camss.c +0 -0

index c54185c93a8a..da4d2213fd3d 100644

drivers/media/platform/qcom/camss/camss.c +230 -0

+	/* CSIPHY0 - clocks/regs/supplies owned by PHY driver */
+	{
+		.csiphy = {
+			.id = 0,
+			.hw_ops = &csiphy_ops_3ph_1_0,
+			.formats = &csiphy_formats_sdm845
+		}
+	},
+	/* CSIPHY1 - clocks/regs/supplies owned by PHY driver */
+	{
+		.csiphy = {
+			.id = 1,
+			.hw_ops = &csiphy_ops_3ph_1_0,
+			.formats = &csiphy_formats_sdm845
+		}
+	},
+	/* CSIPHY2 - clocks/regs/supplies owned by PHY driver */
+	{
+		.csiphy = {
+			.id = 2,
+			.hw_ops = &csiphy_ops_3ph_1_0,
+			.formats = &csiphy_formats_sdm845
+		}
+	},
+	/* CSIPHY3 - clocks/regs/supplies owned by PHY driver */
+	{
+		.csiphy = {
+			.id = 3,
+			.hw_ops = &csiphy_ops_3ph_1_0,
+			.formats = &csiphy_formats_sdm845
+		}
+	},
+};
+
+static const struct camss_subdev_resources csid_res_sm8150[] = {
+	/* CSID0 */
+	{
+		.regulators = {},
+		.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" },
+		.clock_rate = { { 400000000, 480000000, 600000000 },
+				{ 0 },
+				{ 0 },
+				{ 0 } },
+		.reg = { "csid0" },
+		.interrupt = { "csid0" },
+		.csid = {
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID1 */
+	{
+		.regulators = {},
+		.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" },
+		.clock_rate = { { 400000000, 480000000, 600000000 },
+				{ 0 },
+				{ 0 },
+				{ 0 } },
+		.reg = { "csid1" },
+		.interrupt = { "csid1" },
+		.csid = {
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID_LITE0 */
+	{
+		.regulators = {},
+		.clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
+		.clock_rate = { { 400000000, 480000000, 600000000 },
+				{ 0 },
+				{ 0 }, },
+		.reg = { "csid_lite0" },
+		.interrupt = { "csid_lite0" },
+		.csid = {
+			.is_lite = true,
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	},
+	/* CSID_LITE1 */
+	{
+		.regulators = {},
+		.clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
+		.clock_rate = { { 400000000, 480000000, 600000000 },
+				{ 0 },
+				{ 0 }, },
+		.reg = { "csid_lite1" },
+		.interrupt = { "csid_lite1" },
+		.csid = {
+			.is_lite = true,
+			.hw_ops = &csid_ops_gen2,
+			.parent_dev_ops = &vfe_parent_dev_ops,
+			.formats = &csid_formats_gen2
+		}
+	}
+};
+
+/*
+ * cpas_ahb is left at the CAMCC default 80 MHz; it is not matched by
+ * vfe_match_clock_names(). The VFE/VFE-Lite rates are set from the
+ * remaining clock-rate tables.
+ */
+static const struct camss_subdev_resources vfe_res_sm8150[] = {
+	/* VFE0 */
+	{
+		.regulators = {},
+		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+			   "vfe0", "vfe0_axi" },
+		.clock_rate = { { 0 },
+				{ 0 },
+				{ 0 },
+				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+				{ 400000000, 558000000, 637000000, 847000000, 950000000 },
+				{ 0 }, },
+		.reg = { "vfe0" },
+		.interrupt = { "vfe0" },
+		.vfe = {
+			.line_num = 4,
+			.is_lite = false,
+			.has_pd = true,
+			.pd_name = "ife0",
+			.hw_ops = &vfe_ops_170,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE1 */
+	{
+		.regulators = {},
+		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+			   "vfe1", "vfe1_axi" },
+		.clock_rate = { { 0 },
+				{ 0 },
+				{ 0 },
+				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+				{ 400000000, 558000000, 637000000, 847000000, 950000000 },
+				{ 0 }, },
+		.reg = { "vfe1" },
+		.interrupt = { "vfe1" },
+		.vfe = {
+			.line_num = 4,
+			.is_lite = false,
+			.has_pd = true,
+			.pd_name = "ife1",
+			.hw_ops = &vfe_ops_170,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE_LITE_0 */
+	{
+		.regulators = {},
+		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite0" },
+		.clock_rate = { { 0 },
+				{ 0 },
+				{ 0 },
+				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+				{ 320000000, 400000000, 480000000, 600000000 }, },
+		.reg = { "vfe_lite0" },
+		.interrupt = { "vfe_lite0" },
+		.vfe = {
+			.is_lite = true,
+			.line_num = 4,
+			.hw_ops = &vfe_ops_170,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	},
+	/* VFE_LITE_1 */
+	{
+		.regulators = {},
+		.clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite1" },
+		.clock_rate = { { 0 },
+				{ 0 },
+				{ 0 },
+				{ 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+				{ 320000000, 400000000, 480000000, 600000000 }, },
+		.reg = { "vfe_lite1" },
+		.interrupt = { "vfe_lite1" },
+		.vfe = {
+			.is_lite = true,
+			.line_num = 4,
+			.hw_ops = &vfe_ops_170,
+			.formats_rdi = &vfe_formats_rdi_845,
+			.formats_pix = &vfe_formats_pix_845
+		}
+	}
+};
+
+static const struct resources_icc icc_res_sm8150[] = {
+	{
+		.name = "cam_ahb",
+		.icc_bw_tbl.avg = 38400,
+		.icc_bw_tbl.peak = 76800,
+	},
+	{
+		.name = "cam_hf_0_mnoc",
+		.icc_bw_tbl.avg = 2097152,
+		.icc_bw_tbl.peak = 2097152,
+	},
+	{
+		.name = "cam_hf_1_mnoc",
+		.icc_bw_tbl.avg = 2097152,
+		.icc_bw_tbl.peak = 2097152,
+	},
+	{
+		.name = "cam_sf_0_mnoc",
+		.icc_bw_tbl.avg = 2097152,
+		.icc_bw_tbl.peak = 2097152,
+	},
+};
+
  static const struct camss_subdev_resources csiphy_res_8250[] = {
  	/* CSIPHY0 */
  	{

@@ -5725,6 +5942,19 @@ static const struct camss_resources sm6350_resources = {
  	.vfe_num = ARRAY_SIZE(vfe_res_sm6350),
  };
 
+static const struct camss_resources sm8150_resources = {
+	.version = CAMSS_8150,
+	.pd_name = "top",
+	.csiphy_res = csiphy_res_sm8150,
+	.csid_res = csid_res_sm8150,
+	.vfe_res = vfe_res_sm8150,
+	.icc_res = icc_res_sm8150,
+	.icc_path_num = ARRAY_SIZE(icc_res_sm8150),
+	.csiphy_num = ARRAY_SIZE(csiphy_res_sm8150),
+	.csid_num = ARRAY_SIZE(csid_res_sm8150),
+	.vfe_num = ARRAY_SIZE(vfe_res_sm8150),
+};
+
  static const struct camss_resources sm8250_resources = {
  	.version = CAMSS_8250,
  	.pd_name = "top",

@@ -5824,6 +6054,7 @@ static const struct of_device_id camss_dt_match[] = {
  	{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
  	{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
  	{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
+	{ .compatible = "qcom,sm8150-camss", .data = &sm8150_resources },
  	{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
  	{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
  	{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },

drivers/media/platform/qcom/camss/camss.h +1 -0

index 7dc2fd9f03e0..74d8cc2921be 100644
@@ -89,6 +89,7 @@ enum camss_version {
  	CAMSS_8x39,
  	CAMSS_8x53,
  	CAMSS_8x96,
+	CAMSS_8150,
  	CAMSS_8250,
  	CAMSS_8280XP,
  	CAMSS_8300,

Drop csiphy_res_sm8150[], and pull this:

* https://lore.kernel.org/all/[email protected]/

From: Andrew Gigena <[email protected]>

Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera subsystem contains four CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite instances.

The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and VFE 17x implementations; the CSIPHY uses the SC8280XP lane register layout. Add CAMSS_8150 to the version enum and to the shared code paths, then add the per-block clock, regulator, power domain, interrupt and interconnect resources.

The CSIPHY resources are reduced to id/hw_ops/formats only; clocks, regulators, registers and interrupts are owned by the dedicated CSI2 PHY driver.

Signed-off-by Andrew Gigena <[email protected]>

From: Andrew Gigena <[email protected]>

Add SM8150 platform data to the CSI2 DPHY driver so that SM8150 can use the dedicated PHY driver instead of the CAMSS-integrated CSIPHY.

The SM8150 CSIPHY uses the SC8280XP lane register layout, as already used by the CAMSS driver, so reuse that table, dropping the DNP entries, which the new PHY driver does not program. The PHY is fed by the "core" and "timer" clocks, the vdda-phy and vdda-pll supplies, and the Titan top power domain, which is not scaled.

The timer clock is pinned to 300 MHz via a new timer_rate_hz soc field (SM8150 timer only supports 19.2/300 MHz). SM8150 is ordered before X1E80100 as it predates it (7 nm vs 4 nm). A detach of the platform-attached single power domain is done before attaching by name, so single-domain SoCs do not fail with -EEXIST.

Signed-off-by Andrew Gigena <[email protected]>

---
  drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 97 ++++++++++++++++++++++
  drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     | 16 +++-
  drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |  4 +
  3 files changed, 116 insertions(+), 1 deletion(-)

drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +67 -0

index 966d79c98f9b..b8b6589cee35 100644
@@ -45,6 +45,73 @@
  #define CSIPHY_SETTLE_CNT_LOWER_BYTE			2
  #define CSIPHY_SKEW_CAL					7
 
+/* 7nm 2PH v 1.1 2p5Gbps 4 lane DPHY mode */
+static const struct
+mipi_csi2phy_lane_regs lane_regs_sm8150[] = {
+	{.reg_addr = 0x0004, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x002c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0034, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x001c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x003c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0000, .reg_data = 0x90, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0008, .reg_data = 0x0e, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = 0x0010, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0038, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0060, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0064, .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0704, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x072c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0734, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x071c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0714, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0728, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x073c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0700, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0708, .reg_data = 0x0e, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = 0x070c, .reg_data = 0xa5, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0710, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0738, .reg_data = 0x1f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0760, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0764, .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0204, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x022c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0234, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x021c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0214, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x023c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0200, .reg_data = 0x90, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0208, .reg_data = 0x0e, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = 0x0210, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0238, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0260, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0264, .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0404, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x042c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0434, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x041c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x043c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0400, .reg_data = 0x90, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0408, .reg_data = 0x0e, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = 0x0410, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0438, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0460, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0464, .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0604, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x062c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0634, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x061c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0614, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x063c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0600, .reg_data = 0x90, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0608, .reg_data = 0x0e, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{.reg_addr = 0x0610, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0638, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0660, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
+	{.reg_addr = 0x0664, .reg_data = 0x7f, .param_type = CSIPHY_DEFAULT_PARAMS},
+};
+
  /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
  static const struct
  mipi_csi2phy_lane_regs lane_regs_x1e80100[] = {

drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +21 -0

+
+static struct mipi_csi2_genpd sm8150_genpds[] = {
+	{ .name = "top", .scaled = false },
+};
+
+const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sm8150 = {
+	.ops = &phy_qcom_mipi_csi2_ops_3ph_1_0,
+	.reg_info = {
+		.init_seq = lane_regs_sm8150,
+		.lane_array_size = ARRAY_SIZE(lane_regs_sm8150),
+		.common_regs_offset = 0x800,
+	},
+	.supply_names = (const char **)sm8150_supplies,
+	.num_supplies = ARRAY_SIZE(sm8150_supplies),
+	.clk_names = (const char **)sm8150_clks,
+	.num_clk = ARRAY_SIZE(sm8150_clks),
+	.timer_rate_hz = 300000000,
+	.genpds = sm8150_genpds,
+	.num_genpds = ARRAY_SIZE(sm8150_genpds),
+};
+
  static const char * const x1e_clks[] = {
  	"core",
  	"timer",

drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +0 -0

index c0a4fa20eaf0..3a45b8766311 100644

drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +0 -0

  	if (timer_rate <= 0) {
  		ret = -ENODEV;
  		goto unset_opp_rate;

@@ -233,6 +237,15 @@ static int phy_qcom_mipi_csi2_attach_pm_domains(struct mipi_csi2phy_device *csi2
  	const char **pd_names;
  	int i;

drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +1 -0

  	pd_names = devm_kzalloc(csi2phy->dev,
  				sizeof(char *) * csi2phy->soc_cfg->num_genpds,
  				GFP_KERNEL);

@@ -443,6 +456,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)
  }
 
  static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
+	{ .compatible	= "qcom,sm8150-csi2-phy", .data = &mipi_csi2_dphy_sm8150 },
  	{ .compatible	= "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
  	{ }
  };

drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +4 -1

index 7e55ae007370..4da9f12d4f8d 100644
@@ -68,6 +68,9 @@ struct mipi_csi2phy_soc_cfg {
  	const char ** const clk_names;
  	const unsigned int num_clk;
 
+	/* 0 = derive timer rate from link_freq/4; non-zero = fixed rate */
+	unsigned long timer_rate_hz;
+
  	const struct mipi_csi2_genpd *genpds;
  	const unsigned int num_genpds;
  };

@@ -92,6 +95,7 @@ struct mipi_csi2phy_device {
  	u32 hw_version;
  };
 
+extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sm8150;
  extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e;
 
  #endif /* __PHY_QCOM_MIPI_CSI2_H__ */
 
--

2.56.0

Quoted 11 lines

+    /*
+     * platform_probe() auto-attaches a single power domain during probe.
+     * Detach it first so devm_pm_domain_attach_list() can attach all +     * domains by name (otherwise it returns -EEXIST for single-domain +     * SoCs such as SM8150).
+     */
+    if (csi2phy->dev->pm_domain)
+        dev_pm_domain_detach(csi2phy->dev, false);
+

No, there's something in the CPHY series for this already. You'll either have to absorb that patch or apply those changes to your tree and base your stuff off of that, and orchestrate landing this series on top of that series.

What you could do to unblock your series and not have a dependency on another series is cherry-pick the necessary patch.

https://patchwork.linuxtv.org/project/linux-media/patch/[email protected]/

Is there really no AHB clock to be listed here ? Seems again suspect.

These are not the correct names

But why ?