watchdog: tegra: support Tegra20

index adc30da579a..6dc3a3e0b1d 100644
@@ -10,13 +10,105 @@
 #include <wdt.h>
 #include <hang.h>
 #include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
 #include <watchdog.h>
 
 /* Timer registers */
 #define TIMER_PTV			0x0
 #define TIMER_EN			BIT(31)
 #define TIMER_PERIODIC			BIT(30)
+#define TIMER_PTV_MAX			GENMASK(28, 0)
+#define TIMER_PCR			0x4
+#define TIMER_PCR_INTR_CLR		BIT(30)
 
+struct tegra_wdt_priv {
+#if !defined(CONFIG_TEGRA20)
+	void __iomem *wdt_base;
+#endif
+	void __iomem *tmr_base;
+};
+
+#if defined(CONFIG_TEGRA20)
+/*
+ * Tegra20 has no watchdog block. Instead the clock and reset controller can
+ * reset the system when the interrupt of timer 1 or 2 is asserted while the
+ * previous one is still pending.
+ */
+#define T20_WDT_EN			BIT(5)
+#define T20_WDT_SEL_TMR2		BIT(4)
+#define T20_WDT_SYS_RST_EN		BIT(2)
+#define T20_WDT_MASK			(T20_WDT_EN | T20_WDT_SEL_TMR2 | \
+					 T20_WDT_SYS_RST_EN)
+
+/* Use Timer 1 as WDT counter */
+#define T20_WDT_TIMER_BASE		0x0
+
+static int tegra_wdt_reset(struct udevice *dev)
+{
+	struct tegra_wdt_priv *priv = dev_get_priv(dev);
+
+	/*
+	 * Clearing the interrupt alone doesn't restart the timer, so the
+	 * reset could follow as soon as half the timeout after the ping.
+	 * Rewriting the timer setting restarts its period. The register reads
+	 * back the setting (in periodic mode, the timer never clears TIMER_EN),
+	 * and while stopped it holds 0, so pinging doesn't start the timer.
+	 */
+	writel(readl(priv->tmr_base + TIMER_PTV), priv->tmr_base + TIMER_PTV);
+	/*
+	 * Clear the pending interrupt. Doing it after the restart is safe:
+	 * an interrupt from the new period that fired in between is just
+	 * cleared as part of this ping.
+	 */
+	writel(TIMER_PCR_INTR_CLR, priv->tmr_base + TIMER_PCR);
+
+	return 0;
+}
+
+static int tegra_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct tegra_wdt_priv *priv = dev_get_priv(dev);
+	u64 period;
+
+	/*
+	 * The reset occurs on the second expiry of the timer after a ping,
+	 * so the timer period is half of the timeout. The timer has a fixed
+	 * 1 MHz clock and counts PTV + 1 ticks.
+	 */
+	period = timeout * 1000 / 2;
+	if (period < 1 || period > TIMER_PTV_MAX + 1ull)
+		return -EINVAL;
+
+	writel(TIMER_EN | TIMER_PERIODIC | (u32)(period - 1),
+	       priv->tmr_base + TIMER_PTV);
+	/*
+	 * Clear an interrupt left pending from earlier use of the timer,
+	 * which would otherwise reset the system on the first expiry, after
+	 * half the timeout. If the new timer has already expired, this counts
+	 * as a ping, which is harmless right after starting.
+	 */
+	writel(TIMER_PCR_INTR_CLR, priv->tmr_base + TIMER_PCR);
+
+	clrsetbits_le32(&clkrst->crc_rst_src, T20_WDT_MASK,
+			T20_WDT_EN | T20_WDT_SYS_RST_EN);
+
+	return 0;
+}
+
+static int tegra_wdt_stop(struct udevice *dev)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct tegra_wdt_priv *priv = dev_get_priv(dev);
+
+	clrbits_le32(&clkrst->crc_rst_src, T20_WDT_MASK);
+	writel(0, priv->tmr_base + TIMER_PTV);
+	writel(TIMER_PCR_INTR_CLR, priv->tmr_base + TIMER_PCR);
+
+	return 0;
+}
+#else
 /* WDT registers */
 #define WDT_CFG				0x0
 #define WDT_CFG_PERIOD_SHIFT		4

@@ -36,11 +128,6 @@
 #define WDT_TIMER_BASE			0x60
 #define WDT_TIMER_ID			5
 
-struct tegra_wdt_priv {
-	void __iomem *wdt_base;
-	void __iomem *tmr_base;
-};
-
 static int tegra_wdt_reset(struct udevice *dev)
 {
 	struct tegra_wdt_priv *priv = dev_get_priv(dev);

@@ -87,6 +174,7 @@ static int tegra_wdt_stop(struct udevice *dev)
 
 	return 0;
 }
+#endif
 
 static int tegra_wdt_probe(struct udevice *dev)
 {

@@ -97,8 +185,12 @@ static int tegra_wdt_probe(struct udevice *dev)
 	if (!base)
 		return -ENOENT;
 
+#if defined(CONFIG_TEGRA20)
+	priv->tmr_base = base + T20_WDT_TIMER_BASE;
+#else
 	priv->wdt_base = base + WDT_BASE;
 	priv->tmr_base = base + WDT_TIMER_BASE;
+#endif
 
 	return 0;
 }