clk: qcom: Add NSS clock controller support for IPQ5210 SoC
Subsystems (9)
v2 cover clk: qcom: Add NSS clock controller support for IPQ5210 SoC
The NSS (Network Subsystem) clock controller on the IPQ5210 SoC provides clocks and resets to the networking related hardware blocks such as the Packet Process Engine (PPE), the six ports, XGMAC PTP reference clocks, PON, EIP crypto engine, and the SoC-integrated EPHY (2.5G Ethernet PHY). Its parent clocks are sourced from the GCC and CMN PLL blocks.
The NSS NoC clocks are also enabled to use the icc-clk framework, enabling the creation of interconnect paths for the network subsystem's connections with these NoCs.
The patch series is organised as follows:
1/3 dt-bindings + clock/reset/interconnect ID headers for IPQ5210 NSSCC 2/3 NSS clock controller driver for IPQ5210 3/3 DTS: add NSS clock controller node in ipq5210.dtsi
Changes in v2:
- Use RUNTIME_PM_OPS() and pm_ptr() for dev_pm_ops.
- Rebase on next-20261110; drop the CMN PLL DTS patches, which are now
merged.
- Link to v1: https://patch.msgid.link/[email protected]
---
Luo Jie (3):
dt-bindings: clock: qcom: Add NSS clock controller for IPQ5210 SoC
clk: qcom: Add NSS clock controller driver for IPQ5210 SoC
arm64: dts: qcom: ipq5210: Add NSS clock controller node
.../bindings/clock/qcom,ipq9574-nsscc.yaml | 47 +- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 40 + drivers/clk/qcom/Kconfig | 12 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq5210.c | 2202 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq5210-nsscc.h | 106 + include/dt-bindings/interconnect/qcom,ipq5210.h | 18 + include/dt-bindings/reset/qcom,ipq5210-nsscc.h | 60 + 8 files changed, 2483 insertions(+), 3 deletions(-)
---
base-commit: 793807ca13bf3072fc6d16ce6d90e9ab9beff2a5
change-id: 20261104-qcom_ipq5210_nsscc-fe4b2c8d4d18
Best regards,
Signature · 1 line
Luo Jie <[email protected]>
PATCH v2 1/3 dt-bindings: clock: qcom: Add NSS clock controller for IPQ5210 SoC
NSS clock controller provides the clocks and resets to the networking blocks such as PPE (Packet Process Engine), UNIPHY (PCS) and EPHY on IPQ5210 devices.
Add support for the compatible string "qcom,ipq5210-nsscc" based on the existing IPQ9574/IPQ5424 NSS clock controller Device Tree binding. IPQ5210 additionally exposes a pair of EPHY-RAW Rx/Tx clock sources used to derive the clocks for its integrated 2.5G Ethernet PHY, so extend the clocks and clock-names lists with "ephy_rx" and "ephy_tx".
Also add master/slave ids for IPQ5210 networking interfaces, which are used by the nsscc-ipq5210 driver for providing interconnect services using the icc-clk framework.
--- .../bindings/clock/qcom,ipq9574-nsscc.yaml | 47 ++++++++- include/dt-bindings/clock/qcom,ipq5210-nsscc.h | 106 +++++++++++++++++++++ include/dt-bindings/interconnect/qcom,ipq5210.h | 18 ++++ include/dt-bindings/reset/qcom,ipq5210-nsscc.h | 60 ++++++++++++ 4 files changed, 228 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +44 -3
@@ -4,24 +4,28 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ SoCs maintainers: - Bjorn Andersson <[email protected]> + - Luo Jie <[email protected]> description: | Qualcomm networking sub system clock control module provides the clocks, - resets on IPQ9574 and IPQ5424 + resets on IPQ9574, IPQ5424 and IPQ5210 See also: + include/dt-bindings/clock/qcom,ipq5210-nsscc.h include/dt-bindings/clock/qcom,ipq5424-nsscc.h include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq5210-nsscc.h include/dt-bindings/reset/qcom,ipq5424-nsscc.h include/dt-bindings/reset/qcom,ipq9574-nsscc.h properties: compatible: enum: + - qcom,ipq5210-nsscc - qcom,ipq5424-nsscc - qcom,ipq9574-nsscc
@@ -42,6 +46,9 @@ properties: - description: Uniphy2 NSS Rx clock source - description: Uniphy2 NSS Tx clock source - description: GCC NSSCC clock source + - description: CMN_PLL EPHY-RAW Rx clock source + - description: CMN_PLL EPHY-RAW Tx clock source + minItems: 11 '#interconnect-cells': const: 1
@@ -63,6 +70,9 @@ properties: - const: uniphy2_rx - const: uniphy2_tx - const: bus + - const: ephy_rx + - const: ephy_tx + minItems: 11 required: - compatible
@@ -77,6 +87,8 @@ allOf: const: qcom,ipq9574-nsscc then: properties: + clocks: + maxItems: 11 clock-names: items: - const: xo
@@ -90,8 +102,35 @@ allOf: - const: uniphy2_rx - const: uniphy2_tx - const: bus - else: + - if: + properties: + compatible: + const: qcom,ipq5424-nsscc + then: + properties: + clocks: + maxItems: 11 + clock-names: + items: + - const: xo + - const: nss + - const: ppe + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + - if: + properties: + compatible: + const: qcom,ipq5210-nsscc + then: properties: + clocks: + minItems: 13 clock-names: items: - const: xo
@@ -105,6 +144,8 @@ allOf: - const: uniphy2_rx - const: uniphy2_tx - const: bus + - const: ephy_rx + - const: ephy_tx unevaluatedProperties: false
include/dt-bindings/clock/qcom,ipq5210-nsscc.h new file +106 -0
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include/dt-bindings/interconnect/qcom,ipq5210.h new file +18 -0
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* +* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +*/ + +#ifndef INTERCONNECT_QCOM_IPQ5210_H +#define INTERCONNECT_QCOM_IPQ5210_H + +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_EIP 6 +#define SLAVE_NSSNOC_EIP 7 + +#endif /* INTERCONNECT_QCOM_IPQ5210_H */
include/dt-bindings/reset/qcom,ipq5210-nsscc.h new file +60 -0
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Signature · 1 line
2.43.0
PATCH v2 2/3 clk: qcom: Add NSS clock controller driver for IPQ5210 SoC
In reply to Luo JieThe NSS (Network SubSystem) clock controller provides the clocks and resets to the networking blocks such as PPE (Packet Process Engine), UNIPHY (PCS) and the integrated Ethernet PHY on IPQ5210 devices.
The icc-clk framework is used to enable NoC related clocks to create paths so that the networking blocks such as PPE can connect to these NoCs.
--- drivers/clk/qcom/Kconfig | 12 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq5210.c | 2202 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 2215 insertions(+)
drivers/clk/qcom/Kconfig +12 -0
@@ -737,6 +737,18 @@ config IPQ_GCC_9650 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9650. +config IPQ_NSSCC_5210 + tristate "IPQ5210 NSS Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on IPQ_GCC_5210 + default m if ARCH_QCOM + help + Support for NSS clock controller on ipq5210 devices. + NSSCC receives the clock sources from GCC and CMN PLL. + It in turn supplies the clocks and resets to the networking hardware. + Say Y or M if you want to enable networking function on the + IPQ5210 devices. + config IPQ_NSSCC_5424 tristate "IPQ5424 NSS Clock Controller" depends on ARM64 || COMPILE_TEST
drivers/clk/qcom/Makefile +1 -0
@@ -81,6 +81,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_GCC_9650) += gcc-ipq9650.o +obj-$(CONFIG_IPQ_NSSCC_5210) += nsscc-ipq5210.o obj-$(CONFIG_IPQ_NSSCC_5424) += nsscc-ipq5424.o obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
drivers/clk/qcom/nsscc-ipq5210.c new file +2202 -0
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Signature · 1 line
2.43.0
PATCH v2 3/3 arm64: dts: qcom: ipq5210: Add NSS clock controller node
In reply to Luo JieNSS clock controller provides the clocks and resets to the networking hardware blocks on the IPQ5210, such as PPE (Packet Process Engine) and the integrated EPHY.
Note that the CMN PLL output clock names are reversed with respect to the hardware block they actually feed: IPQ5210_PPE_CLK is wired to the NSS hardware block, and IPQ5210_NSS_CLK is wired to the PPE hardware block. Documentation is added in the DTS file to call this out and avoid confusion.
--- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm64/boot/dts/qcom/ipq5210.dtsi +40 -0
@@ -331,6 +331,46 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq5210-nsscc"; + reg = <0x0 0x39b00000 0x0 0x100000>; + /* + * Note: CMN PLL output clock names below are reversed relative + * to the hardware block they feed - IPQ5210_PPE_CLK is wired to + * the NSS hardware block ("nss") and IPQ5210_NSS_CLK is wired + * to the PPE hardware block ("ppe"). + */ + clocks = <&xo_board>, + <&cmn_pll IPQ5210_PPE_CLK>, + <&cmn_pll IPQ5210_NSS_CLK>, + <&gcc GPLL0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>, + <&cmn_pll IPQ5210_EPHY_RAW_CLK>, + <&cmn_pll IPQ5210_EPHY_RAW_CLK>; + clock-names = "xo", + "nss", + "ppe", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus", + "ephy_rx", + "ephy_tx"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; }; timer {
Signature · 1 line
2.43.0