mtd: spi-nor: Micron, Macronix and n25q512ax3 updates

PATCH New Padmarao Begari 1 participant 6 messages Nov 11 Memory technology devices (MTD)

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Padmarao Begari

author

2026-11-11 12:08 UTC #0 lore raw

cover mtd: spi-nor: Micron, Macronix and n25q512ax3 updates

This series updates some Micron, Macronix and n25q512ax3 SPI NOR flashes.

Patches 1-3 enable octal DTR read for the Micron mt35xu01g and mt35xu02g flashes, and apply mt35xu512aba_fixups to all mt35xx flashes with octal DTR read. Patch 2 moves mt35xu01g before mt35xu01gaba, which has the same 3-byte ID, as mt35xu01g is never detected otherwise.

Patch 4 adds the Macronix MX66UM2G45G flash.

Patch 5 disables chip erase for the n25q512ax3 flash, which does not work, so that sector erase is used instead.

Abbarapu Venkatesh Yadav (3):
mtd: spi-nor-ids: Enable octal DTR for mt35xu01g/mt35xu02g
mtd: spi-nor: Use mt35xu512aba fixups for other mt35xx flashes
mtd: spi-nor: Disable chip erase for n25q512ax3 flash

Padmarao Begari (1):
mtd: spi-nor-ids: Match mt35xu01g before mt35xu01gaba

Tejas Bhumkar (1):
mtd: spi-nor: Add Macronix MX66UM2G45G flash

 drivers/mtd/spi/spi-nor-core.c |  6 +++++-
 drivers/mtd/spi/spi-nor-ids.c  | 12 +++++++-----
 2 files changed, 12 insertions(+), 6 deletions(-)

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2.34.1

Padmarao Begari

author

2026-11-11 12:07 UTC #1 lore raw

PATCH 1/5 mtd: spi-nor-ids: Enable octal DTR for mt35xu01g/mt35xu02g

From: Venkatesh Yadav Abbarapu <[email protected]>

Add the SPI_NOR_OCTAL_DTR_READ flag to the Micron mt35xu01g and mt35xu02g flashes. Also move them under CONFIG_SPI_FLASH_MT35XU, so that the driver can apply mt35xu512aba_fixups to them.

Signed-off-by Ashok Reddy Soma <[email protected]>

Signed-off-by Venkatesh Yadav Abbarapu <[email protected]>

Signed-off-by Padmarao Begari <[email protected]>

---
 drivers/mtd/spi/spi-nor-ids.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/mtd/spi/spi-nor-ids.c +3 -3

index 67486d7a945..7be2d950367 100644
@@ -438,11 +438,11 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
 	{ INFO("mt35xu01gaba", 0x2c5b1b, 0,  128 * 1024,  1024,
 		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
-#endif /* CONFIG_SPI_FLASH_MT35XU */
 	{ INFO6("mt35xu01g",  0x2c5b1b, 0x104100, 128 * 1024,  1024,
-		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE | SPI_NOR_OCTAL_DTR_READ) },
 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048,
-		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE | SPI_NOR_OCTAL_DTR_READ) },
+#endif /* CONFIG_SPI_FLASH_MT35XU */
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
 	/* Spansion/Cypress -- single (large) sector size only, at least

Signature · 1 line

2.34.1

Padmarao Begari

author

2026-11-11 12:07 UTC #2 lore raw

PATCH 2/5 mtd: spi-nor-ids: Match mt35xu01g before mt35xu01gaba

In reply to Padmarao Begari

mt35xu01gaba uses the 3-byte ID 2c5b1b, which is also the start of the 6-byte ID of mt35xu01g. As the first matching entry is used, and mt35xu01gaba comes first, mt35xu01g is never detected.

Move mt35xu01g before mt35xu01gaba, so that a flash with the full mt35xu01g ID is detected as mt35xu01g, while any other flash with the ID 2c5b1b is still detected as mt35xu01gaba.

Fixes a3384940edf3 ("mtd: spi-nor: Add mt35xu01gbba octal mode SPI NOR flash")

Signed-off-by Padmarao Begari <[email protected]>

---
 drivers/mtd/spi/spi-nor-ids.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/mtd/spi/spi-nor-ids.c +3 -2

index 7be2d950367..cca053ae9a7 100644
@@ -436,10 +436,11 @@ const struct flash_info spi_nor_ids[] = {
 #ifdef CONFIG_SPI_FLASH_MT35XU
 	{ INFO("mt35xl512aba", 0x2c5a1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
 	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
-	{ INFO("mt35xu01gaba", 0x2c5b1b, 0,  128 * 1024,  1024,
-		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+	/* Must come before mt35xu01gaba, which matches the start of its ID */
 	{ INFO6("mt35xu01g",  0x2c5b1b, 0x104100, 128 * 1024,  1024,
 		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE | SPI_NOR_OCTAL_DTR_READ) },
+	{ INFO("mt35xu01gaba", 0x2c5b1b, 0,  128 * 1024,  1024,
+		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048,
 		USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE | SPI_NOR_OCTAL_DTR_READ) },
 #endif /* CONFIG_SPI_FLASH_MT35XU */

Signature · 1 line

2.34.1

Padmarao Begari

author

2026-11-11 12:07 UTC #3 lore raw

PATCH 3/5 mtd: spi-nor: Use mt35xu512aba fixups for other mt35xx flashes

In reply to Padmarao Begari

From: Venkatesh Yadav Abbarapu <[email protected]>

Apply mt35xu512aba_fixups to the mt35xl512aba, mt35xu01g and mt35xu02g flashes too, not only to mt35xu512aba.

Signed-off-by Ashok Reddy Soma <[email protected]>

Signed-off-by Venkatesh Yadav Abbarapu <[email protected]>

Signed-off-by Padmarao Begari <[email protected]>

---
 drivers/mtd/spi/spi-nor-core.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

drivers/mtd/spi/spi-nor-core.c +5 -1

index c73f2c7c3f8..130c32e7286 100644
@@ -4539,8 +4539,12 @@ void spi_nor_set_fixups(struct spi_nor *nor)
 #endif
 
 #ifdef CONFIG_SPI_FLASH_MT35XU
-	if (!strcmp(nor->info->name, "mt35xu512aba"))
+	if (!strcmp(nor->info->name, "mt35xu512aba") ||
+	    !strcmp(nor->info->name, "mt35xl512aba") ||
+	    !strcmp(nor->info->name, "mt35xu01g") ||
+	    !strcmp(nor->info->name, "mt35xu02g")) {
 		nor->fixups = &mt35xu512aba_fixups;
+	}
 #endif
 
 #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)

Signature · 1 line

2.34.1

Padmarao Begari

author

2026-11-11 12:08 UTC #4 lore raw

PATCH 4/5 mtd: spi-nor: Add Macronix MX66UM2G45G flash

In reply to Padmarao Begari

From: Tejas Bhumkar <[email protected]>

Add the Macronix MX66UM2G45G octal flash. It has been tested in STR mode with erase, write and read back.

Signed-off-by Tejas Bhumkar <[email protected]>

Signed-off-by Padmarao Begari <[email protected]>

---
 drivers/mtd/spi/spi-nor-ids.c | 1 +
 1 file changed, 1 insertion(+)

drivers/mtd/spi/spi-nor-ids.c +1 -0

index cca053ae9a7..ac3765ef7b1 100644
@@ -341,6 +341,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx66l2g45g",  0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
+	{ INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) },
 	{ INFO("mx66lm1g45g",    0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx25lm51245g",   0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },

Signature · 1 line

2.34.1

Padmarao Begari

author

2026-11-11 12:08 UTC #5 lore raw

PATCH 5/5 mtd: spi-nor: Disable chip erase for n25q512ax3 flash

In reply to Padmarao Begari

From: Venkatesh Yadav Abbarapu <[email protected]>

Chip erase does not work on the n25q512ax3 flash, so set NO_CHIP_ERASE to use sector erase instead.

Signed-off-by Tejas Bhumkar <[email protected]>

Signed-off-by Venkatesh Yadav Abbarapu <[email protected]>

Signed-off-by Padmarao Begari <[email protected]>

---
 drivers/mtd/spi/spi-nor-ids.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/mtd/spi/spi-nor-ids.c +1 -1

index ac3765ef7b1..fbcad9b3e60 100644
@@ -427,7 +427,7 @@ const struct flash_info spi_nor_ids[] = {
 		 USE_FSR) },
 	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ INFO6("mt25ql512a",  0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25ql01g",   0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },

Signature · 1 line

2.34.1