fix [id]cache_status for MPC85xx processors
PATCH 1/1 fix [id]cache_status for MPC85xx processors
The existing code for the [id]cache_status commands on MPC85xx processors looks at the wrong bit to determine if the L1 cache is enabled. It looks at the most significant bit when it should look at the least significant bit. This patch corrects this bug. Cheers!
Murray...
CHANGELOG entry:
* Patch by Murray Jensen <[email protected]>, July 19, 2005:
- fix bug in [id]cache_status commands for MPC85xx processors; should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB.
Copyright:
This patch is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
Signature · 19 lines
Murray Jensen, CSIRO Manufacturing & Infra. Tech. Phone: +61 3 9662 7763 Locked Bag No. 9, Preston, Vic, 3072, Australia. Fax: +61 3 9662 7853 Internet: Murray.Jensen at csiro.au To the extent permitted by law, CSIRO does not represent, warrant and/or guarantee that the integrity of this communication has been maintained or that the communication is free of errors, virus, interception or interference. The information contained in this e-mail may be confidential or privileged. Any unauthorised use or disclosure is prohibited. If you have received this e-mail in error, please delete it immediately and notify Murray Jensen on +61 3 9662 7763. Thank you. -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/x-gunzip Size: 306 bytes Desc: 85xx-cache-status-fix.patch.gz Url : http://lists.denx.de/pipermail/u-boot/attachments/20050719/b70aa19b/attachment.bin
Wolfgang Denk
AppliedPATCH 1/1 fix [id]cache_status for MPC85xx processors
Quoted 5 lines · In message <21717.1121697945@gerd> you wrote:
* Patch by Murray Jensen <[email protected]>, July 19, 2005:
- fix bug in [id]cache_status commands for MPC85xx processors; should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB.
Applied, thanks.
Best regards,
Wolfgang Denk
Signature · 5 lines
Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Another Armenia, Belgium ... the weak innocents who always seem to be located on a natural invasion route. -- Kirk, "Errand of Mercy", stardate 3198.4