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FRV FR55x CPU support fixes

PATCH New David Howells 1 participant 1 message Dec 17, 2004

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David Howells

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PATCH 1/1 FRV FR55x CPU support fixes

The attached patch fixes the following issues with support for the FR55x CPUs:

(1) The FR555 has a 64-byte cacheline size; everything else that we've come across has a 32-byte cacheline size.

(2) Fix machine_restart() for FR55x.

(3) Fix frv_cpu_suspend() for FR55x.

Signed-off-by David Howells <[email protected]>
Signed-off-by Mark Salter <[email protected]>

---
warthog>diffstat frv-fr55x-fixes-2610rc3mm1.diff

 arch/frv/Kconfig          |    5 ++++
 arch/frv/kernel/head.S    |    7 +++---
 arch/frv/kernel/process.c |    8 ++++++-
 arch/frv/kernel/setup.c   |    4 +--
 arch/frv/kernel/sleep.S   |   48 +++++++++++++++++++++++++++++++---------------
 include/asm-frv/cache.h   |    4 ++-
 6 files changed, 54 insertions(+), 22 deletions(-)
arch/frv/Kconfig +5 -0
diff -rpuN a/arch/frv/Kconfig b/arch/frv/Kconfig
@@ -202,6 +202,11 @@ config CPU_FR551_COMPILE
 	  This causes appropriate flags to be passed to the compiler to
 	  optimise for the FR555 CPU
 
+config FRV_L1_CACHE_SHIFT
+	int
+	default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
+	default "6" if CPU_FR551
+
 endmenu
 
 choice
arch/frv/kernel/head.S +4 -3
diff -rpuN a/arch/frv/kernel/head.S b/arch/frv/kernel/head.S
@@ -1,6 +1,6 @@
 /* head.S: kernel entry point for FR-V kernel
  *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
+ * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells ([email protected])
  *
  * This program is free software; you can redistribute it and/or

@@ -16,6 +16,7 @@
 #include <asm/page.h>
 #include <asm/spr-regs.h>
 #include <asm/mb86943a.h>
+#include <asm/cache.h>
 #include "head.inc"
 
 ###############################################################################

@@ -194,7 +195,7 @@ __head_do_sdram:
 	bar
 	jmpl		@(gr18,gr0)
 
-	.balign		32
+	.balign		L1_CACHE_BYTES
 __head_move_sdram:
 	cst		gr20,@(gr14,gr0 ),	cc4,#1
 	cst		gr21,@(gr14,gr11),	cc5,#1

@@ -208,7 +209,7 @@ __head_move_sdram:
 	membar
 	jmpl		@(gr19,gr0)
 
-	.balign		32
+	.balign		L1_CACHE_BYTES
 __head_sdram_moved:
 	icul		gr18
 	add		gr18,gr5,gr4
arch/frv/kernel/process.c +7 -1
diff -rpuN a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c
@@ -94,10 +94,16 @@ void cpu_idle(void)
 
 void machine_restart(char * __unused)
 {
+	unsigned long reset_addr;
 #ifdef CONFIG_GDBSTUB
 	gdbstub_exit(0);
 #endif
 
+	if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551)
+		reset_addr = 0xfefff500;
+	else
+		reset_addr = 0xfeff0500;
+
 	/* Software reset. */
 	asm volatile("      dcef @(gr0,gr0),1 ! membar !"
 		     "      sti     %1,@(%0,0) !"

@@ -105,7 +111,7 @@ void machine_restart(char * __unused)
 		     "      nop ! nop ! nop ! nop ! nop ! "
 		     "      nop ! nop ! nop ! nop ! nop ! "
 		     "      nop ! nop ! nop ! nop ! nop ! "
-		     : : "r" (0xfeff0500), "r" (1) );
+		     : : "r" (reset_addr), "r" (1) );
 
 	for (;;)
 		;
arch/frv/kernel/setup.c +2 -2
diff -rpuN a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
@@ -8,7 +8,7 @@
  *  Copyright (C) 1995       Hamish Macdonald
  *  Copyright (C) 2000       Lineo Inc. (www.lineo.com)
  *  Copyright (C) 2001 	     Lineo, Inc. <www.lineo.com>
- *  Copyright (C) 2003 	     David Howells <[email protected]>, Red Hat, Inc.
+ *  Copyright (C) 2003,2004  David Howells <[email protected]>, Red Hat, Inc.
  */
 
 /*

@@ -499,7 +499,7 @@ static void __init determine_cpu(void)
 	case PSR_IMPLE_FR551:
 		cpu_series	= "fr550";
 		cpu_core	= "fr551";
-		pdm_suspend_mode = HSR0_PDM_PLL_STOP;
+		pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR551_MB93555:
arch/frv/kernel/sleep.S +33 -15

84 lines not on this page · raw message

include/asm-frv/cache.h +3 -1
diff -rpuN a/include/asm-frv/cache.h b/include/asm-frv/cache.h
@@ -12,8 +12,10 @@
 #ifndef __ASM_CACHE_H
 #define __ASM_CACHE_H
 
+#include <linux/config.h>
+
 /* bytes per L1 cache line */
-#define L1_CACHE_SHIFT		5
+#define L1_CACHE_SHIFT		(CONFIG_FRV_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
 
 #define __cacheline_aligned	__attribute__((aligned(L1_CACHE_BYTES)))