about memory bandwidth
Hi,How to measure the 60x bus bandwidth.I write a program to write to sdram in a tight loop,every iteration ,i write 8 words, it takes about 36 seconds to finish 32M iterations with i-cache enabled and d-cache disenabled.With d-cache enabled and flushing
cache in every iteration,it takes about 16 seconds.This is below
what i speculated.What is the possible reason?I program the sdram
machine to enable burst mode. 4/7/2000
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Quoted 9 lines · zzh
Hi,How to measure the 60x bus bandwidth.I write a program to write to sdram in a tight loop,every iteration ,i write 8 words, it takes about 36 seconds to finish 32M iterations with i-cache enabled and d-cache disenabled.With d-cache enabled and flushing
cache in every iteration,it takes about 16 seconds.This is below
what i speculated.What is the possible reason?I program the sdram
machine to enable burst mode. 4/7/2000
This is very dependant on the processor and on the exact instructions you use. If you flush the cache (dcbf), then before the next write can proceed the processor has to reload a whole cache line.
Which means that you have at least 2 bus cycles per iteration: the one from the flush and another one to read again. Plus the fact that you might need a sync which may also go the bus.
What do you want to measure exatcly ?
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