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Finalized TODO list for NAND and JFFS...

DISCUSSION Nick 2 participants 3 messages Sep 27, 2000 2 messages not in the archive Memory technology devices (MTD)

lore
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A message that is not in the archive (sent off-list or not yet received): [email protected]

A message that is not in the archive (sent off-list or not yet received): [email protected]

Nick

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#2 lore raw
Quoted 7 lines · David Woodhouse

Also add a checkpointing system or some way of removing the necessity of scanning the whole of the flash on mount.

For a 21MB filesystem, that takes over a minute.

--
dwmw2

By the way, can't we shorten mount time for Intel chips by rewriting read routines in such a way that they don't send Read Status Register command when chip->status is FL_READY?

I think we can. Acually, I have tried already and it shortens mount time dramatically.

So the question, as I can see it, is can we be sure that Status Register has 7th bit set when chip->status == FL_READY?

Any comments?

Nick

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#3 lore raw
Quoted 3 lines · [email protected] said:

By the way, can't we shorten mount time for Intel chips by rewriting
read routines in such a way that they don't send Read Status Register command when chip->status is FL_READY?

Yes - well spotted.

Quoted 2 lines · [email protected] said:

So the question, as I can see it, is can we be sure that Status
Register has 7th bit set when chip->status == FL_READY?

Yes. If that's ever _not_ the case, then consider it a bug in whatever code is setting the state to FL_READY.

Please supply either a SSH public key, so I can give you write access to CVS, or a patch that I can apply. The former is probably better.

--
dwmw2

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#4 lore raw

Please, find the patch attached.

Quoted 14 lines · David Woodhouse
Quoted 3 lines · [email protected] said:

By the way, can't we shorten mount time for Intel chips by rewriting
read routines in such a way that they don't send Read Status Register command when chip->status is FL_READY?

Yes - well spotted.

Quoted 2 lines · [email protected] said:

So the question, as I can see it, is can we be sure that Status
Register has 7th bit set when chip->status == FL_READY?

Yes. If that's ever _not_ the case, then consider it a bug in whatever code is setting the state to FL_READY.

Quoted 7 lines

Please supply either a SSH public key, so I can give you write access to CVS, or a patch that I can apply. The former is probably better.

--
dwmw2

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cfi_cmdset_0001.c +12 -8
@@ -271,15 +271,18 @@
 		/* Remember the status so we know whether to restart
 		   the erase later */
 		suspendedstate = status;
+		map->write16(map, cpu_to_le16(0x00ff), cmd_addr);
+		chip->state = FL_READY;
 		break;
 #if 0
 	case FL_WRITING:
 		/* Not quite yet */
 #endif
 
+	case FL_READY:
+		break;
 	case FL_CFI_QUERY:
 	case FL_JEDEC_QUERY:
-	case FL_READY:
 		map->write16(map, cpu_to_le16(0x0070), cmd_addr);
 		chip->state = FL_STATUS;
 

@@ -306,6 +309,8 @@
 
 			goto retry;
 		}
+		map->write16(map, cpu_to_le16(0x00ff), cmd_addr);
+		chip->state = FL_READY;
 		break;
 
 	default:

@@ -330,9 +335,6 @@
 		goto retry;
 	}
 
-	map->write16(map, cpu_to_le16(0x00ff), cmd_addr);
-	chip->state = FL_READY;
-
 	map->copy_from(map, buf, adr, len);
 
 	if (suspendedstate) {

@@ -1247,15 +1249,18 @@
 		/* Remember the status so we know whether to restart
 		   the erase later */
 		suspendedstate = status;
+		map->write8(map, 0xff, adr);
+		chip->state = FL_READY;
 		break;
 #if 0
 	case FL_WRITING:
 		/* Not quite yet */
 #endif
 
+	case FL_READY:
+		break;
 	case FL_CFI_QUERY:
 	case FL_JEDEC_QUERY:
-	case FL_READY:
 		map->write8(map, 0x70, adr);
 		chip->state = FL_STATUS;
 

@@ -1282,6 +1287,8 @@
 
 			goto retry;
 		}
+		map->write8(map, 0xff, adr);
+		chip->state = FL_READY;
 		break;
 
 	default:

@@ -1305,9 +1312,6 @@
 
 		goto retry;
 	}
-
-	map->write8(map, 0xff, adr);
-	chip->state = FL_READY;
 
 	map->copy_from(map, buf, adr, len);