migration-fixes-2.5.3-pre2-A1
Review
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#define SPURIOUS_APIC_VECTOR 0xff #define ERROR_APIC_VECTOR 0xfe #define INVALIDATE_TLB_VECTOR 0xfd #define RESCHEDULE_VECTOR 0xfc(quoted diff) +2
-1-#define CALL_FUNCTION_VECTOR 0xfb +#define TASK_MIGRATION_VECTOR 0xfb +#define CALL_FUNCTION_VECTOR 0xfa
Are you sure it's a good idea to have 6 interrupts at priority 15? The local apic of the P6 has only one in-service entry and one holding entry for each priority.
I'm not sure what happens if the entries overflow - either an interrupt is lost or the message is resent.
<<<< Newest ia32 docu, vol3, chap. 7.6.4.3:
The P6 family and Pentium processor's local APIC includes an in-service entryy and a holding entry for each priority level. Optimally, software should allocate no more than 2 interrupts per priority. <<<<<
<<< Original PPro, Vol 3, chap 7.4.2:
The processor's local APIC includes an in-service entry and a holding entry for each proirity level. To avoid losing interrupts, software should allocate no more than 2 interrupts per priority. <<<<<
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Manfred
Quoted 4 lines · Manfred Spraul
Quoted 4 lines
#define SPURIOUS_APIC_VECTOR 0xff #define ERROR_APIC_VECTOR 0xfe #define INVALIDATE_TLB_VECTOR 0xfd #define RESCHEDULE_VECTOR 0xfc
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Review
Quoted 4 lines
(quoted diff) +2
-1-#define CALL_FUNCTION_VECTOR 0xfb +#define TASK_MIGRATION_VECTOR 0xfb +#define CALL_FUNCTION_VECTOR 0xfaAre you sure it's a good idea to have 6 interrupts at priority 15? The local apic of the P6 has only one in-service entry and one holding entry for each priority.
we havent been following this strict rule for some time. We are distributing device interrupts according to this rule, but only as an optimization, and only as long as the number of IRQ sources is smaller than ~30.
i think the worst-case is that we might lose a local APIC timer interrupt
- and this only on older APIC versions. Recent CPUs should handle this correctly. AND, we have the local APIC timer interrupt on its own priority level anyway.
So i think the P6 documentation is a pessimisation of the true situation, and that we can very well have multiple interrupts on the same priority level even on older APICs - as long as the local timer interrupt is not amongst them.
Ingo
Quoted 6 lines · Ingo Molnar
So i think the P6 documentation is a pessimisation of the true situation, and that we can very well have multiple interrupts on the same priority level even on older APICs - as long as the local timer interrupt is not amongst them.
You are right.
I tried to reproduce it (force cpu1 to priority 15, send 4 ipis to priority 14 from cpu0, check that all arrive), and it seems that the pIII doesn't drop ipi messages.
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Manfred