P4/Xeon Thermal LVT support (take 4)
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PATCH 1/1 P4/Xeon Thermal LVT support (take 4)
interrupt handler setup has been fixed. Many thanks to Brian, Maciej and Dave for reviewing and help.
Dave if you'd rather one against 2.5-dj-current just drop me a note.
Cheers,
Zwane
arch/i386/kernel/apic.c +3 -0
@@ -449,6 +449,7 @@unsigned int apic_lvterr;unsigned int apic_tmict;unsigned int apic_tdcr; +unsigned int apic_thmr; } apic_pm_state;static void apic_pm_suspend (void *data)
@@ -470,6 +471,7 @@ apic_pm_state.apic_lvterr =apic_read (APIC_LVTERR ); apic_pm_state.apic_tmict =apic_read (APIC_TMICT ); apic_pm_state.apic_tdcr =apic_read (APIC_TDCR ); + apic_pm_state.apic_thmr =apic_read (APIC_LVTTHMR );__save_flags (flags);__cli ();disable_local_APIC ();
@@ -498,6 +500,7 @@apic_write (APIC_SPIV , apic_pm_state.apic_spiv);apic_write (APIC_LVT0 , apic_pm_state.apic_lvt0);apic_write (APIC_LVT1 , apic_pm_state.apic_lvt1); +apic_write (APIC_LVTTHMR , apic_pm_state.apic_thmr);apic_write (APIC_LVTPC , apic_pm_state.apic_lvtpc);apic_write (APIC_LVTT , apic_pm_state.apic_lvtt);apic_write (APIC_TDCR , apic_pm_state.apic_tdcr);
Only in linux-2.5-dj-work/arch/i386/kernel: apic.o
arch/i386/kernel/bluesmoke.c +99 -0
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arch/i386/kernel/i8259.c +4 -0
@@ -95,6 +95,7 @@ BUILD_SMP_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR) BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR) BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR) +BUILD_SMP_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)#endif #define IRQ (x,y) \
@@ -487,6 +488,9 @@/* IPI vectors for APIC spurious and error interrupts */ set_intr_gate (SPURIOUS_APIC_VECTOR , spurious_interrupt);set_intr_gate (ERROR_APIC_VECTOR , error_interrupt); + +/* thermal monitor LVT interrupt */ +set_intr_gate (THERMAL_APIC_VECTOR , thermal_interrupt);#endif /*
include/asm-i386/apicdef.h +11 -1
@@ -71,6 +71,7 @@#define GET_APIC_DEST_FIELD (x) (((x)>>24)&0xFF)#define SET_APIC_DEST_FIELD (x) ((x)<<24)#define APIC_LVTT 0x320 +#define APIC_LVTTHMR 0x330#define APIC_LVTPC 0x340#define APIC_LVT0 0x350#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
@@ -280,7 +281,16 @@u32 __reserved_4[3 ]; } lvt_timer; -/*330*/ struct {u32 __reserved[4 ]; } __reserved_15; +/*330*/ struct {/* LVT - Thermal Sensor */ +u32 vector :8 , + delivery_mode :3 , + __reserved_1 :1 , + delivery_status :1 , + __reserved_2 :3 , + mask :1 , + __reserved_3 :15 ; +u32 __reserved_4[3 ]; + } lvt_thermal;/*340*/ struct {/* LVT - Performance Counter */ u32 vector : 8,
include/asm-i386/hw_irq.h +1 -0
@@ -43,6 +43,7 @@#define RESCHEDULE_VECTOR 0xfc#define CALL_FUNCTION_VECTOR 0xfb +#define THERMAL_APIC_VECTOR 0xf0/* * Local APIC timer IRQ vector is on a different priority level, * to work around the 'lost local interrupt if more than 2 IRQ
include/asm-i386/msr.h +5 -0
@@ -60,6 +60,11 @@#define MSR_P6_EVNTSEL0 0x186#define MSR_P6_EVNTSEL1 0x187 +#define MSR_IA32_THERM_CONTROL 0x19a +#define MSR_IA32_THERM_INTERRUPT 0x19b +#define MSR_IA32_THERM_STATUS 0x19c +#define MSR_IA32_MISC_ENABLE 0x1a0 +#define MSR_IA32_DEBUGCTLMSR 0x1d9#define MSR_IA32_LASTBRANCHFROMIP 0x1db#define MSR_IA32_LASTBRANCHTOIP 0x1dc
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