Skip to contentSkip to conversation

Patch for NEC VR5000 support (part 1 of several for lasat board support)

PATCH Brian Murphy 2 participants 3 messages Jul 2, 2002 MIPS

lore
Share & tools
lore

Brian Murphy

author
#0 lore raw

I have attached a patch which applies to the 2.4 branch and adds support for the NEC VR5000. This would be a first step in adding support for the Lasat architectures.

A comment from someone with cvs commit access would be nice this time.

/Brian

? arch/mips/mm/c-r5000.c

mips/Makefile +3 -0
@@ -78,6 +78,9 @@
 ifdef CONFIG_CPU_R5000
 GCCFLAGS	+= -mcpu=r5000 -mips2 -Wa,--trap
 endif
+ifdef CONFIG_CPU_VR5000
+GCCFLAGS	+= -mcpu=vr5000 -mips2 -Wa,--trap
+endif
 ifdef CONFIG_CPU_R5432
 GCCFLAGS	+= -mcpu=r5000 -mips2 -Wa,--trap
 endif
mips/config.in +2 -0
@@ -324,6 +339,7 @@
 	 R4x00	CONFIG_CPU_R4X00 \
 	 R49XX	CONFIG_CPU_TX49XX \
 	 R5000	CONFIG_CPU_R5000 \
+	 VR5000	CONFIG_CPU_VR5000 \
 	 R5432	CONFIG_CPU_R5432 \
 	 RM7000	CONFIG_CPU_RM7000 \
 	 R52xx	CONFIG_CPU_NEVADA \

@@ -355,6 +371,7 @@
 
 if [ "$CONFIG_CPU_R4X00"  = "y" -o \
      "$CONFIG_CPU_R5000" = "y" -o \
+     "$CONFIG_CPU_VR5000" = "y" -o \
      "$CONFIG_CPU_RM7000" = "y" -o \
      "$CONFIG_CPU_R10000" = "y" -o \
      "$CONFIG_CPU_SB1" = "y" -o \
mips/kernel/Makefile +1 -0
@@ -29,6 +29,7 @@
 obj-$(CONFIG_CPU_R4300)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R4X00)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5000)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_VR5000)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5432)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_RM7000)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_NEVADA)	+= r4k_fpu.o r4k_switch.o
mips/mm/Makefile +1 -0
@@ -21,6 +21,7 @@
 obj-$(CONFIG_CPU_R4X00)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_VR41XX)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R5000)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+obj-$(CONFIG_CPU_VR5000)	+= pg-r4k.o c-r5000.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_NEVADA)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R5432)		+= pg-r5432.o c-r5432.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_RM7000)	+= pg-rm7k.o c-rm7k.o tlb-r4k.o tlbex-r4k.o
mips/mm/loadmmu.c +5 -0
@@ -52,6 +52,7 @@
 
 extern void ld_mmu_r23000(void);
 extern void ld_mmu_r4xx0(void);
+extern void ld_mmu_r5000(void);
 extern void ld_mmu_tx39(void);
 extern void ld_mmu_tx49(void);
 extern void ld_mmu_r5432(void);

@@ -72,6 +73,10 @@
     defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
     defined(CONFIG_CPU_NEVADA)
 		ld_mmu_r4xx0();
+		r4k_tlb_init();
+#endif
+#if defined(CONFIG_CPU_VR5000)
+		ld_mmu_r5000();
 		r4k_tlb_init();
 #endif
 #if defined(CONFIG_CPU_RM7000)

Index: include/asm-mips/cacheops.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/cacheops.h,v retrieving revision 1.1.1.1

asm-mips/cacheops.h +1 -0
diff -u -r1.1.1.1 cacheops.h
@@ -35,6 +35,7 @@
 #define Hit_Writeback_Inv_D	0x15
 					/* 0x16 is unused */
 #define Hit_Writeback_Inv_SD	0x17
+#define Page_Invalidate		0x17
 #define Hit_Writeback_I		0x18
 #define Hit_Writeback_D		0x19
 					/* 0x1a is unused */

Index: include/asm-mips/cpu.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/cpu.h,v
retrieving revision 1.24.2.8

asm-mips/cpu.h +2 -1
diff -u -r1.24.2.8 cpu.h
@@ -53,6 +53,7 @@
 #define PRID_IMP_R4640		0x2200
 #define PRID_IMP_R4650		0x2200		/* Same as R4640 */
 #define PRID_IMP_R5000		0x2300
+#define PRID_IMP_VR5000		0x2300
 #define PRID_IMP_TX49		0x2d00
 #define PRID_IMP_SONIC		0x2400
 #define PRID_IMP_MAGIC		0x2500

@@ -128,7 +129,7 @@
 	CPU_RM7000, CPU_R5432, CPU_4KC, CPU_5KC, CPU_R4310, CPU_SB1,
 	CPU_TX3912, CPU_TX3922, CPU_TX3927, CPU_AU1000, CPU_4KEC, CPU_4KSC,
 	CPU_VR41XX, CPU_R5500, CPU_TX49XX, CPU_TX39XX, CPU_AU1500, CPU_20KC,
-	CPU_LAST
+	CPU_VR5000, CPU_LAST
 };
 
 #endif /* !__ASSEMBLY__ */

Index: include/asm-mips/r4kcache.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/r4kcache.h,v retrieving revision 1.8

asm-mips/r4kcache.h +47 -0

59 lines not on this page · raw message

mips/mm/c-r5000.c new file +528 -0

528 lines not on this page · raw message

#1 lore raw
Quoted 6 lines · Brian Murphy

I have attached a patch which applies to the 2.4 branch and adds support for the NEC VR5000. This would be a first step in adding support for the Lasat architectures.

A comment from someone with cvs commit access would be nice this time.

As NEC's VR5000 is a plain normal R5000 why are you duplicating the processor support with slight variations?

Ralf

author
#2 lore raw
Quoted 6 lines · Ralf Baechle
Quoted 4 lines · Brian Murphy

I have attached a patch which applies to the 2.4 branch and adds support for the NEC VR5000. This would be a first step in adding support for the Lasat architectures.

Quoted 9 lines
Quoted 3 lines

A comment from someone with cvs commit access would be nice this time.

As NEC's VR5000 is a plain normal R5000 why are you duplicating the processor support with slight variations?

Ralf

I believe the problem is in the (lack of) secondary cache support when
the R5000 target is selected in the standard kernel. I thought that making a seperate VR5000 cpu was then a safer option leaving the R5000 as it is and presumably working on the platforms it is used on. I have
no possibility of testing on those platforms to ensure any integration
is successful.

/Brian