Malta board patch

PATCH Carsten Langgaard 3 participants 4 messages Dec 11, 2002 – Dec 12, 2002 MIPS

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Carsten Langgaard

author

2002-12-11 08:34 UTC #0 lore raw

I have attached a patch, with some minor changes for the Malta board.

/Carsten

_    _ ____  ___   Carsten Langgaard   Mailto:[email protected]
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com

Index: arch/mips/mips-boards/generic/memory.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/memory.c,v retrieving revision 1.6.2.1

mips/mips-boards/generic/memory.c +1 -1

diff -u -r1.6.2.1 memory.c
@@ -168,7 +168,7 @@
 			      + boot_mem_map.map[i].size) {
 			ClearPageReserved(virt_to_page(__va(addr)));
 			set_page_count(virt_to_page(__va(addr)), 1);
-			free_page(__va(addr));
+			free_page((unsigned long)__va(addr));
 			addr += PAGE_SIZE;
 			freed += PAGE_SIZE;
 		}

Index: arch/mips/mips-boards/generic/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/pci.c,v retrieving revision 1.5.2.4

mips/mips-boards/generic/pci.c +6 -0

diff -u -r1.5.2.4 pci.c
@@ -405,6 +405,12 @@
 			".set\treorder");
 
 		irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
+		__asm__ __volatile__(
+			".set\tnoreorder\n\t"
+			".set\tnoat\n\t"
+			"sync\n\t"
+			".set\tat\n\t"
+			".set\treorder");
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
 		break;

Index: arch/mips/mips-boards/malta/malta_int.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/malta/malta_int.c,v retrieving revision 1.8.2.6

mips/mips-boards/malta/malta_int.c +3 -1

diff -u -r1.8.2.6 malta_int.c
@@ -91,6 +91,9 @@
 {
         unsigned int data,datahi;
 
+	/* Mask out corehi interrupt. */
+	clear_c0_status(IE_IRQ3);
+
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
         printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);

@@ -125,7 +128,6 @@
 
         /* We die here*/
         die("CoreHi interrupt", regs);
-        while (1) ;
 }
 
 void __init init_IRQ(void)

Index: include/asm-mips/mips-boards/malta.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/mips-boards/malta.h,v retrieving revision 1.1.4.2

asm-mips/mips-boards/malta.h +18 -2

diff -u -r1.1.4.2 malta.h
@@ -32,9 +32,23 @@
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */
-#define MALTA_GT_PORT_BASE      (KSEG1ADDR(0x18000000))
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
 #define MALTA_BONITO_PORT_BASE  (KSEG1ADDR(0x1fd00000))
-#define MALTA_MSC_PORT_BASE     (KSEG1ADDR(0x18000000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	GT_READ(reg, addr);
+	return KSEG1ADDR((addr & 0xffff) << 21);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	MSC_READ(reg, addr);
+	return KSEG1ADDR(addr);
+}
 
 /*
  * Malta RTC-device indirect register access.

@@ -58,5 +72,7 @@
 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
 
 #define SMSC_WRITE(x,a)     outb(x,a)
+
+#define MALTA_JMPRS_REG		(KSEG1ADDR(0x1f000210))
 
 #endif /* !(_MIPS_MALTA_H) */

Index: include/asm-mips64/mips-boards/malta.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/mips-boards/malta.h,v retrieving revision 1.1.2.2

asm-mips64/mips-boards/malta.h +18 -2

diff -u -r1.1.2.2 malta.h
@@ -32,9 +32,23 @@
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */
-#define MALTA_GT_PORT_BASE      (KSEG1ADDR(0x18000000))
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
 #define MALTA_BONITO_PORT_BASE  (KSEG1ADDR(0x1fd00000))
-#define MALTA_MSC_PORT_BASE     (KSEG1ADDR(0x18000000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	GT_READ(reg, addr);
+	return KSEG1ADDR((addr & 0xffff) << 21);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	MSC_READ(reg, addr);
+	return KSEG1ADDR(addr);
+}
 
 /*
  * Malta RTC-device indirect register access.

@@ -58,5 +72,7 @@
 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
 
 #define SMSC_WRITE(x,a)     outb(x,a)
+
+#define MALTA_JMPRS_REG		(KSEG1ADDR(0x1f000210))
 
 #endif /* !(_MIPS_MALTA_H) */

Jun Sun

2002-12-11 17:04 UTC #1 lore raw

A couple of nit-picking points ...

Quoted 10 lines · Carsten Langgaard

Index: arch/mips/mips-boards/generic/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/pci.c,v retrieving revision 1.5.2.4
diff -u -r1.5.2.4 pci.c
mips/mips-boards/generic/pci.c +0 -0
@@ -405,6 +405,12 @@
 			".set\treorder");
 

mips/mips-boards/generic/pci.c line 416

Quoted 10 lines

mips/mips-boards/generic/pci.c +6 -0

 		irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
+		__asm__ __volatile__(
+			".set\tnoreorder\n\t"
+			".set\tnoat\n\t"
+			"sync\n\t"
+			".set\tat\n\t"
+			".set\treorder");
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
 		break;

Would a higher level macro such as __sync or fast_mb be better here?

Quoted 18 lines

Index: arch/mips/mips-boards/malta/malta_int.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/malta/malta_int.c,v retrieving revision 1.8.2.6
diff -u -r1.8.2.6 malta_int.c
mips/mips-boards/malta/malta_int.c +3 -0
@@ -91,6 +91,9 @@
 {
         unsigned int data,datahi;
 
+	/* Mask out corehi interrupt. */
+	clear_c0_status(IE_IRQ3);
+
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
         printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);

mips/mips-boards/malta/malta_int.c line 133

Quoted 7 lines

mips/mips-boards/malta/malta_int.c +0 -1

@@ -125,7 +128,6 @@
 
         /* We die here*/
         die("CoreHi interrupt", regs);
-        while (1) ;
 }
 
 void __init init_IRQ(void)

I think corehi interrupt should be blocked from the beginning. I seem to remember a board errata itme that recommands not using it.

Jun

Maciej W. Rozycki

2002-12-11 17:27 UTC #2 lore raw

Quoted 4 lines · Jun Sun

Quoted 4 lines

mips/mips-boards/generic/pci.c +3 -0

 		irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
+		__asm__ __volatile__(
+			".set\tnoreorder\n\t"
+			".set\tnoat\n\t"

Quoted 8 lines

mips/mips-boards/generic/pci.c line 416
Quoted 6 lines
mips/mips-boards/generic/pci.c +3 -0
+			"sync\n\t"
+			".set\tat\n\t"
+			".set\treorder");
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
 		break;
Would a higher level macro such as __sync or fast_mb be better here?

Fixed by Ralf in the CVS already. :-)

Signature · 3 lines

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: [email protected], PGP key available        +

Carsten Langgaard

author

2002-12-12 07:47 UTC #3 lore raw

In reply to Jun Sun

Quoted 13 lines · Jun Sun

A couple of nit-picking points ...
Quoted 10 lines · Carsten Langgaard
Index: arch/mips/mips-boards/generic/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/pci.c,v retrieving revision 1.5.2.4
diff -u -r1.5.2.4 pci.c
mips/mips-boards/generic/pci.c 11 Dec 2002 08:11:56 -0000 renamed from mips/mips-boards/generic/pci.c 28 Sep 2002 18:28:44 -0000 1.5.2.4 +0 -0
@@ -405,6 +405,12 @@
                      ".set\treorder");
 

Quoted 12 lines

mips/mips-boards/generic/pci.c 11 Dec 2002 08:11:56 -0000 line 416
Quoted 10 lines
mips/mips-boards/generic/pci.c 11 Dec 2002 08:11:56 -0000 renamed from mips/mips-boards/generic/pci.c 28 Sep 2002 18:28:44 -0000 1.5.2.4 +6 -0
              irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
+             __asm__ __volatile__(
+                     ".set\tnoreorder\n\t"
+                     ".set\tnoat\n\t"
+                     "sync\n\t"
+                     ".set\tat\n\t"
+                     ".set\treorder");
              irq &= 0xff;
              BONITO_PCIMAP_CFG = 0;
              break;
Would a higher level macro such as __sync or fast_mb be better here?

I have already send a new patch to Ralf, because he argued for the same thing. These macros was just not around, when I made this fix.

Quoted 25 lines

Quoted 25 lines
Index: arch/mips/mips-boards/malta/malta_int.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/malta/malta_int.c,v retrieving revision 1.8.2.6
diff -u -r1.8.2.6 malta_int.c
mips/mips-boards/malta/malta_int.c 11 Dec 2002 08:11:57 -0000 renamed from mips/mips-boards/malta/malta_int.c 5 Aug 2002 23:53:34 -0000 1.8.2.6 +3 -1
@@ -91,6 +91,9 @@
 {
         unsigned int data,datahi;
 
+     /* Mask out corehi interrupt. */
+     clear_c0_status(IE_IRQ3);
+
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
         printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
@@ -125,7 +128,6 @@
 
         /* We die here*/
         die("CoreHi interrupt", regs);
-        while (1) ;
 }
 

Quoted 5 lines

mips/mips-boards/malta/malta_int.c 11 Dec 2002 08:11:57 -0000 line 133
Quoted 1 line
mips/mips-boards/malta/malta_int.c 11 Dec 2002 08:11:57 -0000 renamed from mips/mips-boards/malta/malta_int.c 5 Aug 2002 23:53:34 -0000 1.8.2.6 +0 -0
 void __init init_IRQ(void)
I think corehi interrupt should be blocked from the beginning. I seem to remember a board errata itme that recommands not using it.

I have found quite a lot of bugs, with the corehi interrupt enabled. It should never happen, so it indicates a fatal error, if it does.
It's true that on an early revision of some PLD code, there was a bug around the corehi interrupt. If you got such a board, I suggest you update your PLD code.

Quoted 2 lines

Jun

_    _ ____  ___   Carsten Langgaard   Mailto:[email protected]
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com