Memory Caching in Interrupt mode

U-Boot-Users Sharad Gupta 6 participants 9 messages Mar 9, 2004 – Mar 10, 2004

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Sharad Gupta

author

2004-03-09 16:33 UTC #0 lore raw

Hi All,

I am using UBoot as a firmware and boot loader for a custom development board based on MPC7455.

I understand UBoot is not intended for use in interrupt modes, but I thought it does no harm in outputting some text on serial console everytime an interrupt comes in, say a timer interrupt (every 1 sec). I am using BDI2000 to start debugging at 0x900. But my problem is that since address translation is turned off while processing interrupts, I am not able to write to the serial port address since processor caches it and does not really push it out to the serial port. I am using ns16550 driver and the serial port is at 0x60000000.

Whats the work around for this problem ?

1. Shall I turn the address translation on, but I am not sure if its safe to do that, and even if I do that where exactly should I do that, in timer_interrupt routine or transfer_to_handler routine ?
2. Or shall i disable the data caches while processing interrupts ?

Thanks
Sharad.

Wolfgang Denk

2004-03-09 17:00 UTC #1 lore raw

Quoted 2 lines · In message <[email protected]> you wrote:

I understand UBoot is not intended for use in interrupt modes, but I

This is not exactly correct. Usually interrupts are not needed and used (to keep the code simple), but nothing prevents you from using interrupts. Even the first examples for U-Boot extensions via standalone programs included a timer interrupt demo.

Quoted 2 lines

thought it does no harm in outputting some text on serial console everytime an interrupt comes in, say a timer interrupt (every 1 sec). I

Works fine here.

Quoted 7 lines

am using BDI2000 to start debugging at 0x900. But my problem is that since address translation is turned off while processing interrupts, I am not able to write to the serial port address since processor caches it and does not really push it out to the serial port. I am using ns16550 driver and the serial port is at 0x60000000.
Whats the work around for this problem ?

Do not enable data cache.

Quoted 1 line

2. Or shall i disable the data caches while processing interrupts ?

Don't enable DC at all.

Best regards,

Wolfgang Denk

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Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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Bruno

2004-03-09 20:28 UTC #2 lore raw

[U-Boot-Users] u-boot support for MPC885

Hello!

I'm new here and I'm actually begginning a development of a board with the MPC885 and I would to use u-boot. But I'm not sure if it supports this processor. Anyone knows if there already is some u-boot development started to support the MPC885??

Best regards,

Bruno

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Wolfgang Denk

2004-03-09 20:59 UTC #3 lore raw

[U-Boot-Users] u-boot support for MPC885

Quoted 4 lines · In message <[email protected]> you wrote:

I'm new here and I'm actually begginning a development of a board with the MPC885 and I would to use u-boot. But I'm not sure if it supports this processor. Anyone

Then start asking yourself simple questions.

Is the MPC885 a member of the MPC8xx family of processors? Yes. Does U-Boot support MPC8xx processors? Yes.

So ythe answer is, yes, U-Boot will be easily adaptable to a MPC885 processor.

Quoted 2 lines

knows if there already is some u-boot development started to support the MPC885??

None that I know of.

Best regards,

Wolfgang Denk

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Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
Life would be so much easier if everyone read the manual.

Yuli Barcohen

2004-03-10 09:06 UTC #4 lore raw

[U-Boot-Users] u-boot support for MPC885

In reply to Bruno

Quoted 1 line

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Bruno writes:

Bruno> I'm new here and I'm actually begginning a development of a Bruno> board with the MPC885 and I would to use u-boot. But I'm not Bruno> sure if it supports this processor. Anyone knows if there Bruno> already is some u-boot development started to support the Bruno> MPC885??

Yes, the U-Boot already supports MPC885 (Duet) family. There is port to MPC885ADS also known as Duet ADS. Look at board/fads and include/configs/DUET_ADS.h

Signature · 4 lines

========================================================================
 Yuli Barcohen       | Phone +972-9-765-1788 |  Software Project Leader
 yuli at arabellasw.com | Fax   +972-9-765-7494 | Arabella Software, Israel
========================================================================

uboot at sundmangroup.com

2004-03-10 15:04 UTC #5 lore raw

[U-Boot-Users] Help :: PQ2FADS / BDI2000

Comrades,
I have the Motorola PQ2FADS reference board and have successfully built Uboot-1.0.2 to it. I also have a BDI2000. When I try to debug the PQ2FADS board with the BDI2000 solely ( by means of e.g TI/TC ) or with ppc82xx_gdb I get a ,

reset detected at 0xfff00124

Always, I can never debug boyond this point due to the reset.

When I run without the BDI2000 , Uboot starts fine. Can someone give me a hint on what I am doing wrong...

Code snippet and point where the Reset is received:
====================================================

_start:

	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH*/
	nop
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x10

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
	b	boot_warm

boot_cold:

#if defined(CONFIG_MPC8260ADS)
	lis	r3, CFG_DEFAULT_IMMR at h
	nop
	lwz	r4, 0(r3)
	nop     <<<----------------------------RESET!!!
	rlwinm	r4, r4, 0, 8, 5

; bdiGDB configuration file for PQ2FADS-ZU board
; ----------------------------------------------
;
[INIT]
; init core register
WREG MSR 0x00001002 ;MSR : ME,RI
WM32 0x0F010004 0xFFFFFFC3 ;SYPCR: disable watchdog
WM32 0x0F0101A8 0x04700000 ;IMMR : internal space @ 0x04700000
WM32 0x04710024 0x100C0001 ;BCR : Single PQ2, ..
WM32 0x04710c94 0x00000001 ;RMR : checkstop reset enable
;
; init memory controller
WM32 0x04710104 0xFF800876 ;OR0: Flash 8MB, CS early negate, 11 w.s.,
Timing relax
WM32 0x04710100 0xFF801801 ;BR0: Flash @0xFF800000, 32bit, no parity
WM32 0x0471010C 0xFFFF8010 ;OR1: BCSR 32KB, all types accesse, 1 w.s.
WM32 0x04710108 0x04501801 ;BR1: BCSR @0x04500000, 32bit, no parity

; init SDRAM Init (PPC bus)
WM16 0x04710184 0x2800 ;MPTPR: Divide Bus clock by 41
WM8 0x0471019C 0x13 ;PSRT : Divide MPTPR output by 20
WM32 0x04710114 0xfe002ec0 ;OR2 : 32MB, 2 banks, row start@A9, 11 rows
WM32 0x04710110 0x00000041 ;BR2 : SDRAM @0x00000000, 64bit, no parity
WM32 0x04710190 0x824b36a3 ;PSDMR: Precharge all banks
WM32 0x04710190 0xaa4b36a3
WM8 0x00000000 0x00 ;Access SDRAM
WM32 0x04710190 0x8a4b36a3 ;PSDMR: CBR Refresh

WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM
WM8	0x00000000	0xFF	        ;Access SDRAM

WM32 0x04710190 0x9a4b36a3 ;PSDMR: Mode Set
WM8 0x00000190 0x00 ;Access SDRAM
WM32 0x04710190 0xc24b36a3 ;PSDMR: enable refresh, normal operation

; init Local Bus SDRAM (100MHz)
WM8 0x047101a4 0x13 ;LSRT
WM32 0x0471011c 0xff803280 ;OR3
WM32 0x04710118 0xd0001861 ;BR3
WM32 0x04710194 0x828737a3 ;LSDMR: Precharge all banks
WM32 0x04710194 0xaa8737a3
WM8 0xd0000000 0x00 ;Access SDRAM
WM32 0x04710194 0x8a8737a3 ;LSDMR: CBR Refresh

WM8	0xd0000000	0xFF	        ;Access SDRAM
WM8	0xd0000000	0xFF	        ;Access SDRAM
WM8	0xd0000000	0xFF	        ;Access SDRAM
WM8	0xd0000000	0xFF	        ;Access SDRAM

WM32 0x04710194 0x9a8737a3 ;LSDMR: Mode Set
WM8 0xd00000cc 0x00 ;Access SDRAM
WM32 0x04710194 0xc28737a3 ;LSDMR: enable refresh, normal operation

;WM16  0xfff00000  0x0060
;WM16  0xfff00000  0x00D0

;WM16 0xfff00000 0xffff

[TARGET]

CPUTYPE     8275        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
BDIMODE     AGENT
STARTUP     RESET
BREAKMODE   HARD
STEPMODE    HWBP
VECTOR CATCH
;MMU XLAT
POWERUP     5000        ;start delay after power-up detected in ms
BOOTADDR    0xfff00100  ;boot address used for start-up break
WORKSPACE   0x04700000	;workspace in target RAM for fast download
MEMDELAY    2000        ;additional memory access delay

[HOST]
IP 134.138.242.88
;FILE E:\cygwin\home\bdidemo\mpc8260\vxworks
;FORMAT ELF
FORMAT ROM
FILE /root/montavista/devrocket/workspace/Uboot/u-boot

;FORMAT      BIN 0x00000000
;FORMAT      BIN 0x04708000
;LOAD        MANUAL      ;load code MANUAL or AUTO after reset
LOAD         AUTO

DEBUGPORT 2001
PROMPT 8275+> ;new prompt for Telnet
;DUMP E:\temp\dump.bin
;DUMP dump.bin ;Linux: dump.bin must already exist and
public writable

| 32 | 64)
WORKSPACE   0x04700000  ;workspace in dual port RAM
FILE         u-boot.bin
;FILE        E:\tornado\target\config\ads8260\test.hex  ;The file to program
;FILE        E:\cygwin\home\bdidemo\mpc8260\vxworks  ;The file to program
;FORMAT      BIN 0xFF900000
FORMAT      BIN 0xFFF00000
;UNLOCK	0xfff00000 0x40000 10
ERASE		0xfff00000
;ERASE       0xFF900000  ;erase sector 4 of flash SIMM (LH28F016SCT)
;ERASE       0xFF940000  ;erase sector 5 of flash SIMM
;ERASE       0xFF980000  ;erase sector 6 of flash SIMM
;ERASE       0xFF9c0000  ;erase sector 7 of flash SIMM

[REGS]
DMM1 0x04700000
FILE reg8280.def

Yuli Barcohen

2004-03-10 17:16 UTC #6 lore raw

[U-Boot-Users] Re:Help :: PQ2FADS / BDI2000

uboot> Comrades, I have the Motorola PQ2FADS reference board and uboot> have successfully built Uboot-1.0.2 to it. I also have a uboot> BDI2000. When I try to debug the PQ2FADS board with the uboot> BDI2000 solely ( by means of e.g TI/TC ) or with ppc82xx_gdb uboot> I get a ,

uboot> reset detected at 0xfff00124

uboot> Always, I can never debug boyond this point due to the reset.

uboot> When I run without the BDI2000 , Uboot starts fine. Can uboot> someone give me a hint on what I am doing wrong...

You put a wrong value (0x4700000) into the IMMR in the BDI configuration file. U-Boot is configured to start with FADS default IMMR (0x0F000000), then it changes it to 0xF0000000 which is acceptable for Linux (unlike 0x4700000). When U-Boot first access the internal RAM using CFG_DEFAULT_IMMR (0x0F000000), bus error and subsequent reset happen because BDI already changed the IMMR.

Signature · 4 lines

========================================================================
 Yuli Barcohen       | Phone +972-9-765-1788 |  Software Project Leader
 yuli at arabellasw.com | Fax   +972-9-765-7494 | Arabella Software, Israel
========================================================================

Doug Kehn

2004-03-10 02:05 UTC #7 lore raw

In reply to Wolfgang Denk

Quoted 9 lines · --- Wolfgang Denk

Quoted 1 line
Whats the work around for this problem ?
Do not enable data cache.
Quoted 1 line
2. Or shall i disable the data caches while
processing interrupts ?
Don't enable DC at all.

As a general rule should the caches (data /
instruction) be enabled or disabled?

I noticed in the MIPS code that the caches were being enabled.

Thanks...

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Wolfgang Denk

2004-03-10 08:12 UTC #8 lore raw

Quoted 3 lines · In message <[email protected]> you wrote:

As a general rule should the caches (data /
instruction) be enabled or disabled?

There is no general rule. It depends on the architecture / processor.

Quoted 2 lines

I noticed in the MIPS code that the caches were being enabled.

If you don't have any on-chip memory or SRAM or so which can be used for intiial data and stack, the "memopry-in-data-cache" trick must be used, and then you obviously have to enable the DC.

IC should always be on.

Best regards,

Wolfgang Denk

Signature · 4 lines

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
A meeting is an event at which the minutes are kept and the hours are
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