440GX PHY/MII access
I don't know of anyway to bypass. You must restrap the PHY to a different address. I used the JTAG interface to disable all PHYs and the 440GX aways responds to address zero.
Carl
Quoted 95 lines · --- Yutao He
Hi Carl,
We have a customized 440GX-based board with only EMAC2 and EMAC3.
And the PHY is using address zero. Yes we've got the problem with the Ethernet interface. Could you please
shed lights on how to by-pass this "un-documented" feature to make EMACS2/3 work?Many thanks,
--Yutao
Quoted 2 lines · Carl Riechers
If you are using address zero for the PHY you will have problems. The 440GX seems to use this
address
Quoted 1 line
for diagnostics. I could not find any
documentation
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on this. I have a simular configuration with only eth2 and eth3. If you are using the Marvel PHYs,
make
Quoted 5 lines
sure you hardware reset them per the specification otherwise the soft reset will not work correctly.
The author of the code was most likely using a different brand of PHY and needed to reset the PHY
to
Quoted 2 lines
have access to certain registers. The code reconfigures the selected MAC to interface with
the
Quoted 1 line
serial bus to the PHYs. Each MAC has a MII serial
bus
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master, but only one can drive the MII serial interface to the PHYs though the bridge.
Carl
Quoted 5 lines · John
Hello,
I am wondering if anyone can illuminate the
following code snippet,
fromppc_440x_eth_init()in
cpu/ppc4xx/440gx_enet.c:Quoted 18 lines
Quoted 18 lines
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); __asm__ volatile ("eieio"); failsafe = 1000; while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); failsafe--; } in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 +
hw_p->hw_addr);Quoted 1 line
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In particular I don't understand the comment
"reset
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emac so we have
access to the phy". In fact, print statements
before and after
the MAC reset indicate that we *can* read PHY
registers before
the MAC reset, but we *lose* the ability to readPHY
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registers
after the MAC reset. Note that this does nothappen
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on all
three boards, and not all the time. Also thisloss
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of PHY-register
access after MAC reset is more likely to happen if the Ethernet cable
is connected.Now, there are a couple oddities: (1) these are
brand-new boards,
still being debugged and flywired; (2) we areusing
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EMACs 2 & 3 over
RGMII, but we have EMACs 0 & 1 not connected to
anything (unlike
the Ocotea board).In particular, I don't doubt that the above code
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is
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correct; certainly
the finger of doubt points in the direction of our new board. Still,
though, I don't yet understand why the MAC reset would cause PHY
access to go away. The scope reveals that afterthe
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MAC reset, the
MDIO line is no longer being driven.Does this ring any bells for anyone?
Thanks.
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