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Dual-Port SRAM

U-Boot-Users Bob White 2 participants 2 messages May 3, 2004

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Bob White

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#0 lore raw

I've got a board with a dual-port SRAM attached to the 440GP on the peripheral bus (at CS1_N). I can map the TLB and access the device from the bdi2000 and the u-boot command prompt (see gigeth.cfg below.)

What configuration is necessary to map this memory into the kernel? Can you point me to some examples? How does it then get accessed from a user program?

Thanks.

================ gigeth.cfg ================
[INIT]
; Setup TLB

WTLB    0xFF000075  0x1FF0003F  ;Flash TLB Entry - 16Mb page
WTLB    0x00000098  0x0000003F  ;SDRAM 256MB @ 0x00000000

; Setup Peripheral Bus
;
; Flash -- 8MB @ FF800000
;
WDCR 0x12 0x00000010 ;Select EBC0_B0AP
WDCR 0x13 0x9B015480 ;B0AP: Flash and SRAM
WDCR 0x12 0x00000000 ;Select EBC0_B0CR
WDCR 0x13 0xFF87A000 ;B0CR: 8MB at 0xFF800000, r/w, 16bit
;
; Dual-port -- 128KB @ FF600000
; -- @ FF700000 CS2_N for Semaphore
;
WDCR 0x12 0x00000011 ;Select EBC0_B1AP
WDCR 0x13 0x9B015480 ;B1AP: Flash and SRAM
WDCR 0x12 0x00000001 ;Select EBC0_B1CR
WDCR 0x13 0xff61e000 ;B1CR: 1MB at 0xFF600000, r/w, 32bit
; (We really only have 128KB, but 1MB ; block is the smallest that we can ; define.)

WDCR 0x12 0x00000012 ;Select EBC0_B2AP
WDCR 0x13 0x9B015480 ;B2AP: Flash and SRAM
WDCR 0x12 0x00000002 ;Select EBC0_B2CR
WDCR 0x13 0xff71e000 ;B2CR: 1MB at 0xFF700000, r/w, 32bit
; (We really map this space to set ; the semaphore connected as CS2_N)

; Setup SDRAM Controller (DDR SDRAM)
WDCR 0x10 0x00000082 ;Select SDRAM0_CLKTR
WDCR 0x11 0x40000000 ;CLKTR: Advance 90 degrees
WDCR 0x10 0x00000080 ;Select SDRAM0_TR0
WDCR 0x11 0x410A4012 ;TR0: V2.0
;WDCR 0x11 0x41054009 ;TR0: V1.0
WDCR 0x10 0x00000081 ;Select SDRAM0_TR1
WDCR 0x11 0x8080082B ;TR1: V2.0
;WDCR 0x11 0x40400800 ;TR1: V1.0
WDCR 0x10 0x00000040 ;Select SDRAM0_B0CR
WDCR 0x11 0x00062001 ;B0CR: 32MByte @ 0x00000000 Mode 2
WDCR 0x10 0x00000030 ;Select SDRAM0_RTR
WDCR 0x11 0x08200000 ;RTR: V2.0
;WDCR 0x11 0x06180000 ;RTR: V1.0
WDCR 0x10 0x00000020 ;Select SDRAM0_CFG0
WDCR 0x11 0x04000000 ;CFG0: 32bit, PMU disable
WDCR 0x11 0x84800000 ;CFG0: enable SDRAM

[TARGET]
JTAGCLOCK 1 ;use 8 MHz JTAG clock
CPUTYPE 440 ;the used target CPU type
;BDIMODE LOADONLY ;the BDI working mode (LOADONLY |
AGENT)
BDIMODE AGENT
BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware
breakpoint
STEPMODE HWBP ;JTAG or HWBP, HWBP uses one or two
hardware breakpoints
;VECTOR CATCH ;catch unhandled exceptions
STARTUP RESET
WORKSPACE 0x00005000

;MMU         XLAT 0xC0000000     ;enable virtual address mode
;PTBASE      0x00000000          ;address where kernel/user stores

pointer to page table
;SIO 7 9600 ;TCP port for serial IO
WAKEUP 1000

[HOST]
;IP 151.120.25.118 ;Linux host

IP          192.168.0.49      ;Windows host
FILE        vmlinux
FORMAT      BIN 0x00000000
START       0x00000000
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DEBUGPORT   2001
DUMP        dump.bin

;DUMP dump.bin ;Linux: dump.bin must already exist
and public writable

[FLASH]
WORKSPACE 0x00004000 ;workspace in SDRAM for fast programming
algorithm
;WORKSPACE 0xFFC00000 ;workspace in SRAM for fast programming
algorithm
CHIPTYPE STRATAX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 |
I28BX8 | I28BX16)
CHIPSIZE 0x800000 ;The size of one flash chip in bytes (e.g.
AM29F040 = 0x80000)
BUSWIDTH 16 ;The width of the flash memory bus in bits (8

| 16 | 32)
FILE        u-boot.bin  ;The file to program
ERASE       0xFFF80000  ;erase U-Boot sector 1
ERASE       0xFFFA0000  ;erase U-Boot sector 2
ERASE       0xFFFE0000  ;erase U-Boot sector 4 (3 is environment)

[REGS]
IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA

IDCR2	0x012	0x013	;EBC0_CFGADDR   and EBC0_CFGDATA
IDCR3	0x014	0x015	;EBM0_CFGADDR   and EBM0_CFGDATA
IDCR4	0x016	0x017	;PPM0_CFGADDR   and PPM0_CFGDATA

FILE reg440gp.def
============================================

Bob

Signature · 17 lines
Robert B. White        Perigee, A Division of Sensis Corp
Software Design Engr   316 Commerce Blvd.
TEL: 315.453.7842x29   Liverpool, NY  13088
FAX: 315.453.7917      www.Perigee.com

------- End of forwarded message -------Bob
-- 
Robert B. White        Perigee, A Division of Sensis Corp
Software Design Engr   316 Commerce Blvd.
TEL: 315.453.7842x29   Liverpool, NY  13088
FAX: 315.453.7917      www.Perigee.com
Bob
-- 
Robert B. White        Perigee, A Division of Sensis Corp
Software Design Engr   316 Commerce Blvd.
TEL: 315.453.7842x29   Liverpool, NY  13088
FAX: 315.453.7917      www.Perigee.com
#1 lore raw
Quoted 4 lines · In message <409670D8.12901.1AF7BA5E@localhost> you wrote:

What configuration is necessary to map this memory into the kernel? Can you point me to some examples? How does it then get accessed from a user program?

You posted the same questions to the PPC mailing list before. Why don't you wait a bit for replies?

And what has this to do with U-Boot? It's off topic here!

Wolfgang Denk

Signature · 4 lines
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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