ppc ep8260 support under 2.6.6

This is basic support for the Embedded Planet's ep8260 board. It doesn't include MTD support. This patch unfortunatly doesn't apply to 2.6.8 just to 2.6.6. The code isn't mine, though it was developed here at Timesys. I just needed it running under 2.6.6.

@@ -223,7 +223,7 @@
    else
        bdp++;
 
-    if (bdp->cbd_sc & BD_ENET_TX_READY) {
+    if (bdp == cbd->dirty_tx) {
        netif_stop_queue(dev);
        cep->tx_full = 1;
    }

@@ -622,6 +622,7 @@
    volatile    scc_enet_t    *ep;
    volatile    immap_t        *immap;
    volatile    iop8260_t    *io;
+    int err;
 
    cp = cpmp;    /* Get pointer to Communication Processor */
 

@@ -198,7 +198,11 @@

#define PB3_TXEN ((uint)0x00020000)
#define PB3_COL ((uint)0x00040000)
#define PB3_CRS ((uint)0x00080000)
+#ifndef CONFIG_EP8260
#define PB3_TXDAT ((uint)0x0f000000)
+#else
+#define PB3_TXDAT ((uint)0x0e000000)
+#endif /* CONFIG_EP8260 */
#define PB3_RXDAT ((uint)0x00f00000)

#define PB3_PSORB0    (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
                PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
@@ -206,7 +210,15 @@
#define PB3_DIRB0    (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
#define PB3_DIRB1    (PB3_TXDAT | PB3_TXEN | PB3_TXER)

-/* CLK15 is receive, CLK16 is transmit. These are board dependent. +#ifdef CONFIG_EP8260

+#define PC3_TXDAT   ((uint)0x00000010)
+#define PC3_PSORC0  (PC3_TXDAT)
+#define PC3_PSORC1  (0)
+#define PC3_DIRC0   (0)
+#define PC3_DIRC1   (PC3_TXDAT)

+#endif /* CONFIG_EP8260 */
+
+/* CLK15 is receive, CLK16 is transmit. These are board dependent.
*/
#define PC_F3RXCLK ((uint)0x00004000)
#define PC_F3TXCLK ((uint)0x00008000)
@@ -219,14 +231,17 @@
/* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
#define PC_MDIO ((uint)0x00000002)
#define PC_MDCK ((uint)0x00000001)
+#elif defined (CONFIG_EP8260)
+#define PC_MDIO ((uint)0x00400000)
+#define PC_MDCK ((uint)0x00200000)
#else
#define PC_MDIO ((uint)0x00000004)
#define PC_MDCK ((uint)0x00000020)
#endif

-/* A table of information for supporting FCCs. This does two things.
+/* A table of information for supporting FCCs. This does two things.
* First, we know how many FCCs we have and they are always externally
- * numbered from zero. Second, it holds control register and I/O
+ * numbered from zero. Second, it holds control register and I/O
* information that could be different among board designs. */
typedef struct fcc_info {
@@ -266,7 +281,7 @@

#ifdef CONFIG_FCC3_ENET
    { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
        (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
-# if defined(CONFIG_TQM8260)
+# if defined(CONFIG_TQM8260) || defined (CONFIG_EP8260)
        PC_MDIO, PC_MDCK },
# else
        0x00000001, 0x00000040 },
@@ -305,7 +320,7 @@
    uint    phy_id_done;
    uint    phy_status;
    phy_info_t    *phy;
-    struct tq_struct phy_task;
+    struct work_struct phy_task;

    uint    sequence_done;

@@ -431,15 +446,20 @@

        printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
               cep->cur_tx, cep->tx_full ? " (full)" : "",
               cep->cur_rx);
+        printk("GFMR %x TSTATE %x TBASE %x TBPTR %x\n",
+               cep->fccp->fcc_gfmr,
+               cep->ep->fen_genfcc.fcc_tstate,
+               cep->ep->fen_genfcc.fcc_tbase,
+               cep->ep->fen_genfcc.fcc_tbptr);
        bdp = cep->tx_bd_base;
-        printk(" Tx @base %p :\n", bdp);
+        printk(" Tx @base %p, dirty %p:\n", bdp, cep->dirty_tx);
        for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
            printk("%04x %04x %08x\n",
                   bdp->cbd_sc,
                   bdp->cbd_datlen,
                   bdp->cbd_bufaddr);
        bdp = cep->rx_bd_base;
-        printk(" Rx @base %p :\n", bdp);
+        printk(" Rx @base %p:\n", bdp);
        for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
            printk("%04x %04x %08x\n",
                   bdp->cbd_sc,
@@ -770,6 +790,18 @@
    volatile struct fcc_enet_private *fep = dev->priv;
    uint s = fep->phy_status;

+#ifdef CONFIG_EP8260
+ /*

+     * Force the ANAR to negotiate half-duplex.     The EP8260 doesn't use
+     * PHY interrupts, and uses its own CPLD to poll the damn thing.  This
+     * ends up taking 128ms to poll reliably.  Instead, we'll just force the
+     * PHY to advertise half-duplex, and miss link status changes.
+     */
+    mii_reg &= ~(0x0140);
+    mii_send_receive (fep->fip, mk_mii_write (MII_REG_ANAR, mii_reg));
+    printk("%s: Forced PHY to half-duplex.\n", dev->name);
+#endif /* CONFIG_EP8260 */
+
    s &= ~(PHY_CONF_SPMASK);

    if (mii_reg & 0x0020)
@@ -1073,8 +1105,9 @@
    printk(".\n");
}

-static void mii_display_config(struct net_device *dev) +static void mii_display_config(void *vdev)
{

+    struct net_device *dev = (struct net_device *) vdev;
    volatile struct fcc_enet_private *fep = dev->priv;
    uint s = fep->phy_status;

@@ -1104,8 +1137,9 @@

    fep->sequence_done = 1;
}

-static void mii_relink(struct net_device *dev)
+static void mii_relink(void *vdev)
{

+    struct net_device *dev = (struct net_device *) vdev;
    struct fcc_enet_private *fep = dev->priv;
    int duplex;

@@ -1128,18 +1162,16 @@

{
    struct fcc_enet_private *fep = dev->priv;

-    fep->phy_task.routine = (void *)mii_relink;
-    fep->phy_task.data = dev;
-    schedule_task(&fep->phy_task);
+    INIT_WORK (&fep->phy_task, mii_relink, dev);
+    schedule_work(&fep->phy_task);

}

static void mii_queue_config(uint mii_reg, struct net_device *dev)

{
    struct fcc_enet_private *fep = dev->priv;

-    fep->phy_task.routine = (void *)mii_display_config;
-    fep->phy_task.data = dev;
-    schedule_task(&fep->phy_task);
+    INIT_WORK (&fep->phy_task, mii_display_config, dev);
+    schedule_work(&fep->phy_task);

}

@@ -1202,6 +1234,7 @@

    }
}

+#if (PHY_INTERRUPT != -1)
/* This interrupt occurs when the PHY detects a link change. */ static irqreturn_t
mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs) @@ -1213,6 +1246,7 @@
mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ return IRQ_HANDLED;
}
+#endif /* (PHY_INTERRUPT != -1) */

#endif /* CONFIG_USE_MDIO */

@@ -1242,7 +1276,7 @@

    ep = (fcc_enet_t *)dev->base_addr;

    if (dev->flags&IFF_PROMISC) {
-   +
        /* Log any net taps. */
        printk("%s: Promiscuous mode enabled.\n", dev->name);
        cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
@@ -1454,6 +1488,16 @@
        io->iop_psorb &= ~PB3_PSORB0;
        io->iop_psorb |= PB3_PSORB1;
        io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);

+#ifdef CONFIG_EP8260
+ /*
+ * The EP8260 uses Port C pins as well...
+ */

+        io->iop_pdirc &= ~PC3_DIRC0;
+        io->iop_pdirc |= PC3_DIRC1;
+        io->iop_psorc &= ~PC3_PSORC0;
+        io->iop_psorc |= PC3_PSORC1;
+        io->iop_pparc |= (PC3_DIRC0 | PC3_DIRC1);
+#endif /* CONFIG_EP8260 */
    }

    /* Port C has clocks......
@@ -1710,11 +1754,11 @@
                            "fenet", dev) < 0)
        printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);

-#ifdef CONFIG_USE_MDIO
+#if defined (CONFIG_USE_MDIO) && (PHY_INTERRUPT != -1)

    if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
                            "mii", dev) < 0)
        printk("Can't get MII IRQ %d\n", fip->fc_interrupt);

-#endif /* CONFIG_USE_MDIO */
+#endif /* CONFIG_USE_MDIO && (PHY_INTERRUPT != -1) */

    /* Set GFMR to enable Ethernet operating mode.
     */

@@ -1749,6 +1793,7 @@
}

#ifdef CONFIG_USE_MDIO
+#ifndef CONFIG_EP8260 /* EP8260 uses wierd CPLD setup to communicate with PHY */ /* MII command/status interface.
* I'm not going to describe all of the details. You can find the
* protocol definition in many other places, including the data sheet
@@ -1845,6 +1890,133 @@

    return retval;
}
+#else /* CONFIG_EP8260 */
+
+#define SET_WRITE_OP(reg)   (*(reg) &= ~0x04)
+#define SET_READ_OP(reg)    (*(reg) |=    0x05)
+#define SET_CLOCK_HIGH(reg) (*(reg) |=    0x02)
+#define SET_CLOCK_LOW(reg)  (*(reg) &= ~0x02)
+#define SET_DATA_ON(reg)    (*(reg) |=    0x01)
+#define SET_DATA_OFF(reg)   (*(reg) &= ~0x01)
+#define GET_DATA_BIT(reg)   (*(reg) &    0x01)

+
+/* MII command/status interface.
+ * I'm not going to describe all of the details. You can find the
+ * protocol definition in many other places, including the data sheet
+ * of most PHY parts.
+ *
+ * The MDCLK and MDIO bits are accessed through a board control register
+ * on the EP8260...
+ */
+static uint
+mii_send_receive(fcc_info_t *fip, uint cmd)
+{
+#define LCL_DELAY 1000

+    uint        retval;
+    int            read_op, i;
+    static spinlock_t    mii_lock = SPIN_LOCK_UNLOCKED;
+    static volatile unsigned char *phyControl = NULL;

+
+ spin_lock (&mii_lock);
+
+ if (phyControl == NULL)
+ phyControl = ioremap (0xFA000004, 1);
+

+    if ((*phyControl & 0xc0) != 0xc0) {
+    *phyControl |= 0xc0;
+    udelay (500);
+    }
+
+    /* When we get here, both clock and data are high, outputs.
+     * Output is open drain.
+     * Data transitions on high->low clock, is valid on low->high clock.
+     * Spec says edge transitions no closer than 160 nSec, minimum clock
+     * cycle 400 nSec.    I could only manage about 500 nSec edges with
+     * an XOR loop, so I won't worry about delays yet.
+     * I disable interrupts during bit flipping to ensure atomic
+     * updates of the registers.  I do lots of interrupt disable/enable
+     * to ensure we don't hang out too long with interrupts disabled.
+     */
+
+    /*
+     * First, crank out 32 1-bits as preamble.
+     * This is 64 transitions to clock the bits, with clock/data
+     * left high.
+     */
+    SET_WRITE_OP (phyControl);
+    SET_DATA_ON (phyControl);
+    for (i=0; i<32; i++) {
+    SET_CLOCK_LOW (phyControl);
+    udelay(LCL_DELAY);
+    SET_CLOCK_HIGH (phyControl);
+    udelay(LCL_DELAY);
+    }

+
+ read_op = ((cmd & 0xf0000000) == 0x60000000);
+
+ /* We return the command word on a write op, or the command portion

+     * plus the new data on a read op.    This is what the 8xx FEC does,
+     * and it allows the functions to simply look at the returned value
+     * and know the PHY/register as well.
+     */
+    if (read_op)
+    retval = (cmd >> 16);
+    else
+    retval = cmd;
+
+    /* Clock out the first 16 MS bits of the command.
+    */
+    SET_WRITE_OP (phyControl);
+    for (i=0; i<16; i++) {
+    SET_CLOCK_LOW (phyControl);
+    udelay(LCL_DELAY);
+    if (cmd & 0x80000000)
+        SET_DATA_ON (phyControl);
+    else
+        SET_DATA_OFF (phyControl);
+    cmd <<= 1;
+    SET_CLOCK_HIGH (phyControl);
+    udelay(LCL_DELAY);
+    }

+
+ /* For read, clock in 16 bits. For write, clock out
+ * rest of command.
+ */
+ if (read_op) {
+ for (i=0; i<16; i++) {
+ SET_READ_OP (phyControl);
+ udelay(LCL_DELAY);
+

+        SET_CLOCK_LOW (phyControl);
+        udelay(LCL_DELAY);
+        retval <<= 1;
+        retval |= GET_DATA_BIT (phyControl);
+        SET_CLOCK_HIGH (phyControl);
+        udelay(LCL_DELAY);
+    }
+    }
+    else {
+    for (i=0; i<16; i++) {
+        SET_CLOCK_LOW (phyControl);
+        if (cmd & 0x80000000)
+        SET_DATA_ON (phyControl);
+        else
+        SET_DATA_OFF (phyControl);
+        cmd <<= 1;
+        SET_CLOCK_HIGH (phyControl);
+        udelay(LCL_DELAY);

+ }
+ }
+
+ spin_unlock (&mii_lock);
+

+    /* We exit with the same conditions as entry.
+    */
+    return(retval);

+#undef LCL_DELAY
+}
+
+#endif /* CONFIG_EP8260 */

static void
fcc_stop(struct net_device *dev)
@@ -1895,6 +2067,9 @@

            schedule();

        mii_do_cmd(dev, fep->phy->startup);
+#ifdef CONFIG_EP8260
+        fep->link = 1;
+#endif
        netif_start_queue(dev);
        return 0;        /* Success */
    }

@@ -1905,4 +2080,3 @@
return 0; /* Always succeed */
#endif /* CONFIG_USE_MDIO */
}
-

@@ -475,7 +475,7 @@
            if (break_pressed && info->line == sercons.index) {
                if (ch != 0 && time_before(jiffies,
                            break_pressed + HZ*5)) {
-                    handle_sysrq(ch, regs, NULL, NULL);
+                    handle_sysrq(ch, regs, tty);
                    break_pressed = 0;
                    goto ignore_char;
                } else

@@ -1867,6 +1867,9 @@
    DECLARE_WAITQUEUE(wait, current);
    struct serial_state *state = info->state;

#endif
+#ifdef SERIAL_DEBUG_OPEN
+ struct serial_state *state = info->state;
+#endif

    int        retval;
    int        do_clocal = 0;

@@ -2519,6 +2522,10 @@

    volatile    smc_uart_t    *up;
    volatile    scc_t        *scp;
    volatile    scc_uart_t    *sup;
+#ifdef SCC_CONSOLE
+      volatile    scc_t        *scp;
+      volatile    scc_uart_t    *sup;
+#endif
    volatile    immap_t        *immap;
    volatile    iop8260_t    *io;

@@ -493,6 +493,9 @@

config SPRUCE
bool "IBM-Spruce"

+config EP8260
+ bool "Embedded Planet EP8260"
+
config LOPEC
bool "Motorola-LoPEC"

@@ -502,6 +505,9 @@
config MVME5100

    bool "Motorola-MVME5100"

+config MVME5500
+ bool "Motorola-MVME5500"
+
config PPLUS
bool "Motorola-PowerPlus"

@@ -573,9 +579,9 @@
default y

config 8260
- bool "MPC8260 CPM Support" if WILLOW
+ bool "MPC8260 CPM Support" if WILLOW || EP8260
depends on 6xx

-    default y if TQM8260 || RPXSUPER || EST8260 || SBS8260
+    default y if TQM8260 || RPXSUPER || EST8260 || SBS8260 || EP8260

help
The MPC8260 CPM (Communications Processor Module) is a typical embedded CPU made by Motorola. Selecting this option means that

@@ -226,7 +226,7 @@
    blt    2b

3: blr

- .section ".relocate_code","xa"
+ .section "._relocate_code","xa"
/*
* Flush and enable instruction cache
* First, flush the data cache in case it was enabled and may be

@@ -29,7 +29,7 @@
    *(.text)
    *(.fixup)
    __relocate_start = .;
-    *(.relocate_code)
+    *(._relocate_code)
    __relocate_end = .;
  }
  _etext = .;

@@ -22,6 +22,7 @@

# misc-$(CONFIG_MACHINE) variable.

boot := arch/ppc/boot
+sboot := $(TOPDIR)/arch/ppc/boot
common := $(boot)/common
utils := $(boot)/utils
bootlib := $(boot)/lib
@@ -55,6 +56,13 @@

         end-$(CONFIG_EMBEDDEDBOOT)    := embedded
        misc-$(CONFIG_EMBEDDEDBOOT)    := misc-embedded.o

+      zimage-$(CONFIG_EP8260)        := zImage-IMAGE
+zimageinitrd-$(CONFIG_EP8260)        := zImage.initrd-IMAGE
+    znetboot-$(CONFIG_EP8260)        := zImage.bin
+  znetbootrd-$(CONFIG_EP8260)        := zImage.initrd.bin
+   tftpimage-$(CONFIG_EP8260)        := /tftpboot/zImage.initrd.$(end-y)
+        misc-$(CONFIG_EP8260)        := misc-embedded.o
+
      zimage-$(CONFIG_EBONY)        := zImage-TREE
zimageinitrd-$(CONFIG_EBONY)        := zImage.initrd-TREE
         end-$(CONFIG_EBONY)        := ebony

@@ -79,8 +87,7 @@

# kconfig 'feature', only one of these will ever be 'y' at a time.
# The rest will be unset.
-motorola := $(CONFIG_MCPN765)$(CONFIG_MVME5100)$(CONFIG_PRPMC750) \
-$(CONFIG_PRPMC800)$(CONFIG_LOPEC)$(CONFIG_PPLUS)
+motorola := $(CONFIG_MCPN765)$(CONFIG_MVME5100)$(CONFIG_PRPMC750)$(CONFIG_PRPMC800)$(CONFIG_LOPEC)$(CONFIG_PPLUS)
motorola := $(strip $(motorola))
pcore := $(CONFIG_PCORE)$(CONFIG_POWERPMC250)

@@ -125,7 +132,7 @@
AFLAGS_head.o += $(cacheflag-y)

# Linker args. This specifies where the image will be run at.
-LD_ARGS := -T $(boot)/ld.script \

+LD_ARGS                := -T $(sboot)/ld.script \
                   -Ttext $(CONFIG_BOOT_LOAD) -Bstatic

OBJCOPY_ARGS := -O elf32-powerpc

@@ -160,7 +167,7 @@

targets := dummy.o

-$(obj)/zvmlinux: $(OBJS) $(LIBS) $(boot)/ld.script $(images)/vmlinux.gz \

+$(obj)/zvmlinux: $(OBJS) $(LIBS) $(sboot)/ld.script $(images)/vmlinux.gz \
        $(obj)/dummy.o
    $(OBJCOPY) $(OBJCOPY_ARGS) \
        --add-section=.image=$(images)/vmlinux.gz \

@@ -170,7 +177,7 @@
$(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \
-R .stabstr -R .ramdisk -R .sysmap

-$(obj)/zvmlinux.initrd: $(OBJS) $(LIBS) $(boot)/ld.script \

+$(obj)/zvmlinux.initrd: $(OBJS) $(LIBS) $(sboot)/ld.script \
        $(images)/vmlinux.gz $(obj)/dummy.o
    $(OBJCOPY) $(OBJCOPY_ARGS) \
        --add-section=.ramdisk=$(images)/ramdisk.image.gz \
@@ -219,6 +226,12 @@
    $(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y)
    $(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot

+$(images)/zImage-IMAGE: $(obj)/zvmlinux
+ $(OBJCOPY) -O binary $(obj)/zvmlinux $(images)/zImage.bin
+
+$(images)/zImage.initrd-IMAGE: $(obj)/zvmlinux.initrd
+ $(OBJCOPY) -O binary $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bin
+
$(images)/zImage-UBOOT: $(images)/vmlinux.gz $(MKIMAGE)

    $(MKIMAGE) -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
        -n 'Linux-$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)' \

@@ -16,6 +16,7 @@

#ifdef CONFIG_8260
#include <asm/mpc8260.h>
#include <asm/immap_8260.h>
+static void clk_8260(bd_t *bd);
#endif
#ifdef CONFIG_40x
#include <asm/io.h>
@@ -96,7 +97,7 @@
#endif /* CONFIG_MBX */

#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || \

-    defined(CONFIG_RPX6) || defined(CONFIG_EP405)
+    defined(CONFIG_RPX6) || defined(CONFIG_EP405) || defined (CONFIG_EP8260)

/* Helper functions for Embedded Planet boards.
*/
/* Because I didn't find anything that would do this....... @@ -146,7 +147,7 @@

    }
}

-#ifdef CONFIG_RPX6
+#if defined (CONFIG_RPX6) || defined (CONFIG_EP8260) static uint
rpx_baseten(u_char *cp)
{
@@ -216,7 +217,7 @@
}
#endif

-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405)
+#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405) || defined (CONFIG_EP8260)

static void
rpx_memsize(bd_t *bd, u_char *cp)
{
@@ -333,6 +334,84 @@
}
#endif /* RPXLITE || RPXCLASSIC */

+#ifdef CONFIG_EP8260
+void
+embed_config(bd_t **bdp)
+{

+    u_char  *cp;
+    u_char  eebuf[256];
+    bd_t    *bd;

+
+ memcpy (eebuf, (void *) *bdp, 256);
+
+ bd = &bdinfo;
+ *bdp = bd;
+
+ /* We look for two things, the Ethernet address and the

+     * serial baud rate.  The records are separated by
+     * newlines.
+     */

+ cp = eebuf + 1;
+ while (*cp != 0x0A)
+ {
+ if (*cp == 'E') {
+ cp++;
+ if (*cp == 'A') {
+ cp += 2;
+ rpx_eth(bd, cp);
+ }
+ }
+ if (*cp == 'S') {
+ cp++;
+ if (*cp == 'B') {
+ cp += 2;
+ bd->bi_baudrate = rpx_baseten(cp);
+ }
+ }
+ if (*cp == 'D') {
+ cp++;
+ if (*cp == '1') {
+ cp += 2;
+ rpx_memsize(bd, cp);
+ }
+ }
+ if (*cp == 'X') {
+ cp++;
+ if (*cp == 'T') {

+                cp += 2;
+                bd->bi_busfreq = rpx_baseten(cp);
+                clk_8260 (bd);

+ }
+ }
+ if (*cp == 'N') {
+ cp++;
+ if (*cp == 'V') {
+ cp += 2;
+ bd->bi_nvram_size = rpx_baseten(cp) * 1024;
+ }
+ }
+ /*
+ * Scan to the end of the record.
+ */
+ while (*cp != 0x0A)
+ cp++;
+
+ /*
+ * If the next character is a 0x0A, we are done.
+ */
+ cp++;
+ }
+
+ bd->bi_memstart = 0;
+ bd->bi_immr = 0xF0000000;
+
+ if (bd->bi_memsize == 0)
+ bd->bi_memsize = 64 * (1024 * 1024);
+
+ bd->bi_intfreq = 165000000;
+}
+#endif /* CONFIG_EP8260 */
+
#ifdef CONFIG_BSEIP
/* Build a board information structure for the BSE ip-Engine.
* There is more to come since we will add some environment

@@ -57,7 +57,7 @@
    isync

#endif

-#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
+#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP) || defined (CONFIG_EP8260)

mr r29,r3 /* On the MBX860, r3 is the board info pointer.
* On the RPXSUPER, r3 points to the NVRAM
* configuration keys.
@@ -129,7 +129,7 @@

    mr    r3, r29

#endif

-#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
+#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP) || defined (CONFIG_EP8260)

mr r4,r29 /* put the board info pointer where the relocate
* routine will find it
*/

@@ -108,7 +108,7 @@
    mtlr    r6
    b    flush_instruction_cache
 
-    .section ".relocate_code","xa"
+    .section "._relocate_code","xa"
   

do_relocate:

    /* We have 2 cases --- start < load, or start > load

@@ -1085,9 +1085,13 @@
    lwzx    r0,r6,r4
    stwx    r0,r6,r3
    bdnz    3b
+#ifndef CONFIG_PPC_NO_DCACHE
    dcbst    r6,r3            /* write it to memory */
+#endif /* CONFIG_PPC_NO_DCACHE */
    sync
+#ifndef CONFIG_PPC_NO_ICACHE
    icbi    r6,r3            /* flush the icache line */
+#endif /* CONFIG_PPC_NO_ICACHE */
    cmplw    0,r6,r5
    blt    4b
    sync                /* additional sync needed on g4 */

@@ -1124,9 +1128,13 @@
    lwz     r15,0(r14)               /* instruction, now insert top */
    rlwimi  r15,r10,16,16,31         /* half of vp const in low half */
    stw    r15,0(r14)               /* of instruction and restore. */
+#ifndef CONFIG_PPC_NO_DCACHE
    dcbst    r0,r14             /* write it to memory */
+#endif /* CONFIG_PPC_NO_DCACHE */
    sync
+#ifndef CONFIG_PPC_NO_ICACHE
    icbi    r0,r14             /* flush the icache line */
+#endif /* CONFIG_PPC_NO_ICACHE */
    cmpw    r12,r13
    bne     1b
    sync                /* additional sync needed on g4 */

@@ -1158,9 +1166,13 @@
    lwz     r15,0(r14)               /* instruction, now insert top */
    rlwimi  r15,r11,16,16,31         /* half of pv const in low half*/
    stw    r15,0(r14)               /* of instruction and restore. */
+#ifndef CONFIG_PPC_NO_DCACHE
    dcbst    r0,r14             /* write it to memory */
+#endif /* CONFIG_PPC_NO_DCACHE */
    sync
+#ifndef CONFIG_PPC_NO_ICACHE
    icbi    r0,r14             /* flush the icache line */
+#endif /* CONFIG_PPC_NO_ICACHE */
    cmpw    r12,r13
    bne     1b
 

@@ -1655,7 +1667,7 @@
    andc    r11, r11, r10
    mtspr    HID0, r11
    isync
-    li    r5, MSR_ME|MSR_RI
+    li    r5, MSR_ME|MSR_IP|MSR_RI
    lis    r6,2f@h
    addis    r6,r6,-KERNELBASE@h
    ori    r6,r6,2f@l

@@ -30,6 +30,7 @@

obj-$(CONFIG_PREP_RESIDUAL) += residual.o
obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o

obj-$(CONFIG_EST8260)        += est8260_setup.o
+obj-$(CONFIG_EP8260)        += ep8260_setup.o
obj-$(CONFIG_TQM8260)        += tqm8260_setup.o
obj-$(CONFIG_EV64260)        += ev64260_setup.o

obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o

@@ -34,11 +34,11 @@

obj-$(CONFIG_POWER4) += open_pic2.o

obj-$(CONFIG_PPC_CHRP)        += open_pic.o indirect_pci.o i8259.o
obj-$(CONFIG_PPC_PREP)        += open_pic.o indirect_pci.o i8259.o todc_time.o
+obj-$(CONFIG_GT64260)        += gt64260_common.o gt64260_pic.o

obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
-obj-$(CONFIG_EV64260) += gt64260_common.o gt64260_pic.o \
- indirect_pci.o todc_time.o pci_auto.o
+obj-$(CONFIG_EV64260) += indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
pci_auto.o
@@ -63,6 +63,7 @@
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o ppc8260_pic.o
+obj-$(CONFIG_EP8260) += todc_time.o todc_nvram.o
ifeq ($(CONFIG_PPC_GEN550),y)
obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o
obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o

@@ -70,6 +70,70 @@

#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v))

/*
+ * For reading and writing 64-bit values, we need to use the floating point
+ * registers. The code will enable MSR_FP in the MSR register, use FPR1 to
+ * read from and write to memory, and then restore everything to the
+ * previous values.
+ */
+static inline unsigned long long __raw_readll (int addr)
+{

+    unsigned long flags;
+    unsigned long msr;
+    unsigned long msr_save;
+    unsigned long long result;
+    unsigned long long fp_save;
+
+    local_irq_save (flags);
+    asm volatile ("sync\n"
+                  "mfmsr    %0\n"
+                  "ori        %1,%0,0x2000\n"
+                  "mtmsr    %1\n"
+                  "isync\n"
+                  "stfdx    1,0,%2\n"
+                  "lfdx        1,0,%4\n"
+                  "stfdx    1,0,%3\n"
+                  "sync\n"
+                  "lfdx        1,0,%2\n"
+                  "mtmsr    %0\n"
+                  "sync\n"
+                  "isync\n"
+                  : "=&r" (msr_save), "=&r" (msr)
+                  : "r" (&fp_save), "r" (&result), "r" (addr)
+                  : "memory" );

+ local_irq_restore (flags);
+
+ return result;
+}
+
+static inline void __raw_writell (unsigned long long value, int addr) +{

+    unsigned long flags;
+    unsigned long msr;
+    unsigned long msr_save;
+    unsigned long long fp_save;
+
+    local_irq_save (flags);
+    asm volatile ("sync\n"
+                  "mfmsr    %0\n"
+                  "ori        %1,%0,0x2000\n"
+                  "mtmsr    %1\n"
+                  "isync\n"
+                  "stfdx    1,0,%2\n"
+                  "lfdx        1,0,%3\n"
+                  "stfdx    1,0,%4\n"
+                  "sync\n"
+                  "lfdx        1,0,%2\n"
+                  "mtmsr    %0\n"
+                  "sync\n"
+                  "isync\n"
+                  : "=&r" (msr_save), "=&r" (msr)
+                  : "r" (&fp_save), "r" (&value), "r" (addr)
+                  : "memory" );

+ local_irq_restore (flags);
+ return;
+}
+
+/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in

@@ -16,6 +16,10 @@

#include <platforms/est8260.h>
#endif

+#ifdef CONFIG_EP8260
+#include <platforms/ep8260.h>
+#endif
+
#ifdef CONFIG_SBS8260
#include <platforms/sbs8260.h>
#endif

@@ -34,6 +34,13 @@
    unsigned int nvram_data;
 
    /*
+     * Following are start and stop indexes for valid NVRAM data access.
+     * These are used by todc_nvram.c.
+     */
+    unsigned int nvdata_start;
+    unsigned int nvdata_stop;
+
+    /*
     * Define bits to stop external set of regs from changing so
     * the chip can be read/written reliably.
     */

@@ -98,6 +105,7 @@

#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */

#define TODC_TYPE_DS17285        12    /* Dallas DS17285 RTC */
+#define TODC_TYPE_DS1556        13    /* Dallas DS1556 RTC */

#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */

/*
@@ -208,6 +216,28 @@

#define    TODC_TYPE_DS1501_NVRAM_ADDR_REG    0x10
#define    TODC_TYPE_DS1501_NVRAM_DATA_REG    0x13

+#define    TODC_TYPE_DS1556_NVRAM_SIZE        0x7fff0
+#define    TODC_TYPE_DS1556_SW_FLAGS        0
+#define    TODC_TYPE_DS1556_YEAR            0x1ffff
+#define    TODC_TYPE_DS1556_MONTH            0x1fffe
+#define    TODC_TYPE_DS1556_DOM            0x1fffd    /* Day of Month */
+#define    TODC_TYPE_DS1556_DOW            0x1fffc    /* Day of Week */
+#define    TODC_TYPE_DS1556_HOURS            0x1fffb
+#define    TODC_TYPE_DS1556_MINUTES        0x1fffa
+#define    TODC_TYPE_DS1556_SECONDS        0x1fff9
+#define    TODC_TYPE_DS1556_CNTL_B            0x1fff9
+#define    TODC_TYPE_DS1556_CNTL_A            0x1fff8    /* control_a R/W regs */
+#define    TODC_TYPE_DS1556_WATCHDOG        0x1fff7
+#define    TODC_TYPE_DS1556_INTERRUPTS        0x1fff6
+#define    TODC_TYPE_DS1556_ALARM_DATE        0x1fff5
+#define    TODC_TYPE_DS1556_ALARM_HOUR        0x1fff4
+#define    TODC_TYPE_DS1556_ALARM_MINUTES        0x1fff3
+#define    TODC_TYPE_DS1556_ALARM_SECONDS        0x1fff2
+#define    TODC_TYPE_DS1556_CENTURY        0x1fff8
+#define    TODC_TYPE_DS1556_FLAGS            0x1fff0
+#define    TODC_TYPE_DS1556_NVRAM_ADDR_REG        0
+#define    TODC_TYPE_DS1556_NVRAM_DATA_REG        0
+
#define    TODC_TYPE_DS1557_NVRAM_SIZE        0x7fff0
#define    TODC_TYPE_DS1557_SW_FLAGS        0
#define    TODC_TYPE_DS1557_YEAR            0x7ffff
@@ -448,6 +478,8 @@
                                    \
    todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;    \
    todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;    \
+    todc_info->nvdata_start  = 0;                     \
+    todc_info->nvdata_stop   = 0;                     \

}

extern todc_info_t *todc_info;

Note the reason it doesn't apply is that ep8260 (rpx8260) went into 2.6.8. :)

If you have access to the board, could you give it a shot in the linuxppc-2.5 tree? There's fcc changes in there that I'd like to get tested on a few more boards before I push them out (or the driver gets obsoleted).

Tom Rini
http://gate.crashing.org/~trini/

That's even better. :)

Unfortunately I don't have bitkeeper access. Is there a tar ball of the ppc tree? I didn't find one the last time I went looking.

Greg Weeks

There isn't one. There is however, rsync.
rsync://source.mvista.com::linuxppc-2.5

Tom Rini
http://gate.crashing.org/~trini/