powerpc merge (headers)

diff -Nru --exclude=.svn xenomai-orig/include/nucleus/asm-powerpc/atomic.h xenomai-devel/include/nucleus/asm-powerpc/atomic.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (C) 2003,2004 Philippe Gerum <[email protected]>.
+ * 
+ * 64-bit PowerPC adoption
+ *   copyright (C) 2005 Taneli V������h������kangas and Heikki Lindholm
+ *
+ * Xenomai is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License,
+ * or (at your option) any later version.
+ *
+ * Xenomai is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Xenomai; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ */
+
+#ifndef _XENO_ASM_POWERPC_ATOMIC_H
+#define _XENO_ASM_POWERPC_ATOMIC_H
+
+#ifdef CONFIG_PPC64
+static __inline__ void atomic_set_mask(unsigned long mask,
+				       unsigned long *ptr)
+{
+    __asm__ __volatile__ ("\n\
+1:	ldarx	5,0,%0 \n\
+	or	5,5,%1\n"
+"	stdcx.	5,0,%0 \n\
+	bne-	1b"
+	: /*no output*/
+	: "r" (ptr), "r" (mask)
+	: "r5", "cc", "memory");
+}
+
+static __inline__ void atomic_clear_mask(unsigned long mask,
+					 unsigned long *ptr)
+{
+    __asm__ __volatile__ ("\n\
+1:	ldarx	5,0,%0 \n\
+	andc	5,5,%1\n"
+"	stdcx.	5,0,%0 \n\
+	bne-	1b"
+	: /*no output*/
+	: "r" (ptr), "r" (mask)
+	: "r5", "cc", "memory");
+}
+#endif /* CONFIG_PPC64 */
+
+#include <asm/atomic.h>
+
+#ifdef __KERNEL__
+
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#define atomic_xchg(ptr,v)       xchg(ptr,v)
+#define atomic_cmpxchg(ptr,o,n)  cmpxchg(ptr,o,n)
+#define xnarch_memory_barrier()  smp_mb()
+
+ /* These are defined in arch/ppc/kernel/misc.S on 32-bit PowerPC */
+void atomic_set_mask(unsigned long mask, unsigned long *ptr);
+void atomic_clear_mask(unsigned long mask, unsigned long *ptr);
+
+#define xnarch_atomic_set(pcounter,i)          atomic_set(pcounter,i)
+#define xnarch_atomic_get(pcounter)            atomic_read(pcounter)
+#define xnarch_atomic_inc(pcounter)            atomic_inc(pcounter)
+#define xnarch_atomic_dec(pcounter)            atomic_dec(pcounter)
+#define xnarch_atomic_inc_and_test(pcounter)   atomic_inc_and_test(pcounter)
+#define xnarch_atomic_dec_and_test(pcounter)   atomic_dec_and_test(pcounter)
+#define xnarch_atomic_set_mask(pflags,mask)    atomic_set_mask(mask,pflags)
+#define xnarch_atomic_clear_mask(pflags,mask)  atomic_clear_mask(mask,pflags)
+
+#else /* !__KERNEL__ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb)	"dcbt " #ra "," #rb ";"
+#else
+#define PPC405_ERR77(ra,rb)
+#endif
+
+#ifdef CONFIG_SMP
+#define EIEIO_ON_SMP    "eieio\n"
+#define ISYNC_ON_SMP    "\n\tisync"
+#else
+#define EIEIO_ON_SMP
+#define ISYNC_ON_SMP
+#endif
+
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ *
+ * (lifted from linux/include/asm-powerpc/system.h)
+ */
+
+static __inline__ unsigned long 
+    __xchg_u32(volatile void *p, unsigned long val)
+{
+    unsigned long prev;
+    
+    __asm__ __volatile__(
+    EIEIO_ON_SMP
+"1: lwarx	%0,0,%2 \n"
+    PPC405_ERR77(0,%2)
+"   stwcx.	%3,0,%2 \n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
+    : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
+    : "cc", "memory");
+    
+    return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+    __xchg_u64(volatile void *p, unsigned long val)
+{
+    unsigned long prev;
+    
+    __asm__ __volatile__(
+    EIEIO_ON_SMP
+"1: ldarx	%0,0,%2 \n"
+    PPC405_ERR77(0,%2)
+"   stdcx.	%3,0,%2 \n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
+    : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
+    : "cc", "memory");
+
+    return prev;
+}
+#endif
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid xchg().
+ */
+extern void __xnarch_xchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+    __xchg(volatile void *ptr, unsigned long x, unsigned int size)
+{
+    switch (size) {
+    case 4:
+	return __xchg_u32(ptr, x);
+#ifdef CONFIG_PPC64
+    case 8:
+	return __xchg_u64(ptr, x);
+#endif
+    }
+    __xnarch_xchg_called_with_bad_pointer();
+    return x;
+}
+
+#define atomic_xchg(ptr,x) \
+    ({                                                                         \
+	__typeof__(*(ptr)) _x_ = (x);                                          \
+	(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr)));\
+    })
+
+/*
+ * Compare and exchange - if *p == old, set it to new,
+ * and return the old value of *p.
+ *
+ * (lifted from linux/include/asm-powerpc/system.h)
+ */
+static __inline__ unsigned long
+    __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long n)
+{
+    unsigned int prev;
+
+    __asm__ __volatile__ (
+    EIEIO_ON_SMP
+"1: lwarx	%0,0,%2		# __cmpxchg_u32\n\
+    cmpw	0,%0,%3\n\
+    bne-	2f\n"
+    PPC405_ERR77(0,%2)
+"   stwcx.	%4,0,%2\n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    "\n\
+2:"
+    : "=&r" (prev), "=m" (*p)
+    : "r" (p), "r" (old), "r" (n), "m" (*p)
+    : "cc", "memory");
+
+    return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __inline__ unsigned long
+    __cmpxchg_u64(volatile long *p, unsigned long old, unsigned long n)
+{
+    unsigned long prev;
+
+    __asm__ __volatile__ (
+    EIEIO_ON_SMP
+"1: ldarx	%0,0,%2		# __cmpxchg_u64\n\
+    cmpd	0,%0,%3\n\
+    bne-	2f\n\
+    stdcx.	%4,0,%2\n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    "\n\
+2:"
+    : "=&r" (prev), "=m" (*p)
+    : "r" (p), "r" (old), "r" (n), "m" (*p)
+    : "cc", "memory");
+
+    return prev;
+}
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __xnarch_cmpxchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+    __cmpxchg(volatile void *ptr, unsigned long old, unsigned long n,
+		unsigned int size)
+{
+    switch (size) {
+    case 4:
+	return __cmpxchg_u32(ptr, old, n);
+#ifdef CONFIG_PPC64
+    case 8:
+	return __cmpxchg_u64(ptr, old, n);
+#endif
+    }
+    __xnarch_cmpxchg_called_with_bad_pointer();
+    return old;
+}
+
+#define atomic_cmpxchg(ptr,o,n) \
+    ({									\
+	__typeof__(*(ptr)) _o_ = (o);					\
+	__typeof__(*(ptr)) _n_ = (n);					\
+	(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,	\
+	(unsigned long)_n_, sizeof(*(ptr)));				\
+    })
+
+
+/*
+ * Atomic operations lifted from linux/include/asm-powerpc/atomic.h 
+ * (currently asm-ppc64/atomic.h exposes these)
+ */
+#ifndef CONFIG_PPC64
+static __inline__ void atomic_inc(atomic_t *v)
+{
+    int t;
+
+    __asm__ __volatile__(
+"1: lwarx	%0,0,%2		# atomic_inc\n\
+    addic	%0,%0,1\n"
+    PPC405_ERR77(0,%2)
+"   stwcx.	%0,0,%2 \n\
+    bne-	1b"
+    : "=&r" (t), "=m" (v->counter)
+    : "r" (&v->counter), "m" (v->counter)
+    : "cc");
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+    int t;
+
+    __asm__ __volatile__(
+    EIEIO_ON_SMP
+"1: lwarx	%0,0,%1		# atomic_inc_return\n\
+    addic	%0,%0,1\n"
+    PPC405_ERR77(0,%1)
+"   stwcx.	%0,0,%1 \n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    : "=&r" (t)
+    : "r" (&v->counter)
+    : "cc", "memory");
+
+    return t;
+}
+
+static __inline__ void atomic_dec(atomic_t *v)
+{
+    int t;
+
+    __asm__ __volatile__(
+"1: lwarx	%0,0,%2		# atomic_dec\n\
+    addic	%0,%0,-1\n"
+    PPC405_ERR77(0,%2)\
+"   stwcx.	%0,0,%2\n\
+    bne-	1b"
+    : "=&r" (t), "=m" (v->counter)
+    : "r" (&v->counter), "m" (v->counter)
+    : "cc");
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+    int t;
+
+    __asm__ __volatile__(
+    EIEIO_ON_SMP
+"1: lwarx	%0,0,%1		# atomic_dec_return\n\
+    addic	%0,%0,-1\n"
+    PPC405_ERR77(0,%1)
+"   stwcx.	%0,0,%1\n\
+    bne-	1b"
+    ISYNC_ON_SMP
+    : "=&r" (t)
+    : "r" (&v->counter)
+    : "cc", "memory");
+
+    return t;
+}
+#endif /* CONFIG_PPC64 */
+
+/*
+ * Atomic mask operations from linux/arch/ppc/kernel/misc.S
+ * (for 64-bit PowerPC already defined above)
+ */
+#ifndef CONFIG_PPC64
+static __inline__ void atomic_set_mask(unsigned long mask,
+				       unsigned long *ptr)
+{
+    __asm__ __volatile__ ("\n\
+1:	lwarx	5,0,%0 \n\
+	or	5,5,%1\n"
+	PPC405_ERR77(0,%0) \
+"	stwcx.	5,0,%0 \n\
+	bne-	1b"
+	: /*no output*/
+	: "r" (ptr), "r" (mask)
+	: "r5", "cc", "memory");
+}
+
+static __inline__ void atomic_clear_mask(unsigned long mask,
+					 unsigned long *ptr)
+{
+    __asm__ __volatile__ ("\n\
+1:	lwarx	5,0,%0 \n\
+	andc	5,5,%1\n"
+	PPC405_ERR77(0,%0) \
+"	stwcx.	5,0,%0 \n\
+	bne-	1b"
+	: /*no output*/
+	: "r" (ptr), "r" (mask)
+	: "r5", "cc", "memory");
+}
+#endif /* CONFIG_PPC64 */
+
+#define xnarch_memory_barrier()  __asm__ __volatile__("": : :"memory")
+
+#define xnarch_atomic_set(pcounter,i)          (((pcounter)->counter) = (i))
+#define xnarch_atomic_get(pcounter)            ((pcounter)->counter)
+#define xnarch_atomic_inc(pcounter)            atomic_inc(pcounter)
+#define xnarch_atomic_dec(pcounter)            atomic_dec(pcounter)
+#define xnarch_atomic_inc_and_test(pcounter)   (atomic_inc_return(pcounter) == 0)
+#define xnarch_atomic_dec_and_test(pcounter)   (atomic_dec_return(pcounter) == 0)
+#define xnarch_atomic_set_mask(pflags,mask)    atomic_set_mask(mask,pflags)
+#define xnarch_atomic_clear_mask(pflags,mask)  atomic_clear_mask(mask,pflags)
+
+#define cpu_relax()  xnarch_memory_barrier()
+
+#endif /* __KERNEL__ */
+
+typedef atomic_t atomic_counter_t;
+typedef unsigned long atomic_flags_t;
+
+#define xnarch_atomic_xchg(ptr,x) atomic_xchg(ptr,x)
+#define xnarch_atomic_cmpxchg(ptr,o,n) atomic_cmpxchg(ptr,o,n)
+
+#endif /* !_XENO_ASM_POWERPC_ATOMIC_H */

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diff -Nru --exclude=.svn xenomai-orig/include/nucleus/asm-powerpc/uart.h xenomai-devel/include/nucleus/asm-powerpc/uart.h
@@ -0,0 +1,35 @@
+/**
+ * @file
+ * This file is part of the Xenomai project.
+ *
+ * @note Copyright (C) 2004 Philippe Gerum <[email protected]> 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _XENO_ASM_POWERPC_UART_H
+#define _XENO_ASM_POWERPC_UART_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_SANDPOINT)
+
+#define TTYS0  { 0xfe0003f8, 4 }
+#define TTYS1  { 0xfe0002f8, 3 }
+#else
+#error "UART configuration is undefined for this PowerPC platform"
+#endif
+
+#endif /* !_XENO_ASM_POWERPC_UART_H */

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diff -Nru --exclude=.svn xenomai-orig/include/nucleus/asm-ppc/uart.h xenomai-devel/include/nucleus/asm-ppc/uart.h

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