SMP Design

Hi,
I am working on a symmetric multiprocessing(SMP) based board design. Now, I am into feasibility analysis. Here are my queries
What qualifies a CPU to be capable of SMP?
Hardware cache coherency
test-and-set, compare-and-swap or load-link/ store-conditional
instructions.
Unique Id(read this in Intel MP specs) Is it required for
powerpc-smp?
CPU-local interrupt controller (intel specific) Is it required
for powerpc-smp
OpenPIC, interrupt routing

what are the other points that support SMP for a CPU. I read that ppc 603 won't support pure SMP.

I am searching for the "considerations for SMP design using powerpc processors" please provide pointers for the same.

Can I find any reference design for SMP boards? I am interested architecture part, interrupt routing and OpenPIC stuff. I find it hard to find information on SMP board design.

Waiting for your response.

Thanks and Regards,
Suresh Chandra Mannava.