atyfb: Set ECP divider
PATCH 13/18 atyfb: Set ECP divider
From: Ville Syrjälä <[email protected]>
Set ECP (scaler/overlay clock) divider. The limits were taken from the XFree86 ati driver.
Signed-off-by Ville Syrjälä <[email protected]>
Signed-off-by Antonino Daplas <[email protected]>
---
drivers/video/aty/atyfb.h | 1 drivers/video/aty/atyfb_base.c | 86 +++++++++++++++++++++------------------- drivers/video/aty/mach64_ct.c | 17 +++++++- 3 files changed, 61 insertions(+), 43 deletions(-)
drivers/video/aty/atyfb.h +1 -0
@@ -50,6 +50,7 @@ struct pll_info {int sclk, mclk, mclk_pm, xclk;int ref_div;int ref_clk; +int ecp_max; }; typedef struct {
drivers/video/aty/atyfb_base.c +46 -40
139 lines not on this page · raw message
drivers/video/aty/mach64_ct.c +14 -3
@@ -206,9 +206,7 @@ static int aty_valid_pll_ct(const struct {u32 q;struct atyfb_par *par = (struct atyfb_par *) info->par; -#ifdef DEBUG int pllvclk; -#endif /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ q = par->ref_clk_per * pll->pll_ref_div *4 / vclk_per;
@@ -223,13 +221,26 @@ static int aty_valid_pll_ct(const struct pll->vclk_post_div_real = postdividers[pll->vclk_post_div];// pll->vclk_post_div <<= 6; pll->vclk_fb_div = q * pll->vclk_post_div_real /8 ; -#ifdef DEBUG pllvclk = (1000000 *2 * pll->vclk_fb_div) / (par->ref_clk_per * pll->pll_ref_div); +#ifdef DEBUG printk ("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n" , __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real);#endif pll->pll_vclk_cntl =0x03 ;/* VCLK = PLL_VCLK/VCLKx_POST */ + +/* Set ECP (scaler/overlay clock) divider */ +if (par->pll_limits.ecp_max) { +int ecp = pllvclk / pll->vclk_post_div_real; +int ecp_div =0 ; + +while (ecp > par->pll_limits.ecp_max && ecp_div <2 ) { + ecp >>=1 ; + ecp_div++; + } + pll->pll_vclk_cntl |= ecp_div <<4 ; + } +return 0 ; }
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