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regarding ata_piix initialization trouble

DISCUSSION Tejun 3 participants 4 messages Feb 23, 2006 libata

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Tejun

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Hello, Jean & 0602.

I was digging ICH docs to reimplement ata_piix initialization and found out that 6300ESB lists high bits (the present bits) of PCS register as reserved. But they indiciate that the bits might change anytime just as in other docs. I think something went wrong with those bits in that particular chipset and Intel decided to ignore the bits.

I'm wondering whether your problems are related to this. Can you guys please run 'lspci -n' on your machines which had the piix initialization trouble and report the result here?

Thanks a lot.

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tejun
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Quoted 5 lines · Tejun

Hello, Jean & 0602.

I was digging ICH docs to reimplement ata_piix initialization and found out that 6300ESB lists high bits (the present bits) of PCS register as reserved. But they indiciate that the bits might change anytime just as in other docs. I think something went wrong with those bits in that particular chipset and Intel decided to ignore the bits.

I'm wondering whether your problems are related to this. Can you guys please run 'lspci -n' on your machines which had the piix initialization trouble and report the result here?

Note that we still get the PCS bits wrong because, e.g. they only apply to ports 0 and 2 on some chipsets, not ports 0 and 1 like you would expect.

Jeff

#3 lore raw
In reply to Tejun
Quoted 8 lines · Tejun

Hello, Jean & 0602.

I was digging ICH docs to reimplement ata_piix initialization and found out that 6300ESB lists high bits (the present bits) of PCS register as reserved. But they indiciate that the bits might change anytime just as in other docs. I think something went wrong with those bits in that particular chipset and Intel decided to ignore the bits.

I'm wondering whether your problems are related to this. Can you guys please run 'lspci -n' on your machines which had the piix initialization trouble and report the result here?

Thanks a lot.

Hi,

here is the result:
00:00.0 Class 0600: 8086:3592 (rev 0c) 00:00.1 Class ff00: 8086:3593 (rev 0c) 00:02.0 Class 0604: 8086:3595 (rev 0c) 00:03.0 Class 0604: 8086:3596 (rev 0c) 00:1c.0 Class 0604: 8086:25ae (rev 02) 00:1e.0 Class 0604: 8086:244e (rev 0a) 00:1f.0 Class 0601: 8086:25a1 (rev 02) 00:1f.2 Class 0101: 8086:25a3 (rev 02) 00:1f.3 Class 0c05: 8086:25a4 (rev 02) 02:00.0 Class 0200: 11ab:4361 (rev 17) 03:07.0 Class 0100: 11ab:6081 (rev 07) 04:02.0 Class 0300: 1002:4752 (rev 27) 04:03.0 Class 0200: 8086:1076 (rev 05)

Regards,

r.

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#2 lore raw
In reply to Jeff Garzik
Quoted 11 lines · Jeff Garzik
Quoted 5 lines · Tejun

Hello, Jean & 0602.

I was digging ICH docs to reimplement ata_piix initialization and found out that 6300ESB lists high bits (the present bits) of PCS register as reserved. But they indiciate that the bits might change anytime just as in other docs. I think something went wrong with those bits in that particular chipset and Intel decided to ignore the bits.

I'm wondering whether your problems are related to this. Can you guys please run 'lspci -n' on your machines which had the piix initialization trouble and report the result here?

Note that we still get the PCS bits wrong because, e.g. they only apply to ports 0 and 2 on some chipsets, not ports 0 and 1 like you would expect.

Jeff, can you please elaborate? I'm currently looking at datasheets for ICH5, 6, 7 and 6300ESB but can't really understand what you're saying. Doesn't PCS + MAP give the whole picture?

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tejun