Longhaul - Use hardware support
PATCH 1/1 Longhaul - Use hardware support
Hardware is stopping bus masters. There is no need to implement this in Linux kernel. I tested it really hard. Even doing md5sum on my files before and after. No corruption. 2 days without even single lockup. No "dma broken" messages. My system: Epia M10000 (CLE266 chipset) with VIA Nehemiah 1GHz.
Changes in Kconfig:
1. ACPI_PROCESSOR - this code need ACPI C3 state working,
2. !X86_UP_APIC - (un)patched "longhaul" isn't APIC compatible,
3. !SMP - (un)patched "longhaul" isn't SMP compatible. First step would be APIC support. Second - per CPU private data.
Changes in longhaul.h:
- clock tables merged - differences are little, "longhaul" will do errata for detected CPU,
- eblcr tables merged - reason above,
- format of voltage tables changed,
- added mobile vrm.
Changes in longhaul.c:
- most important - now C3 state is causing transition,
- code resopnsible for clearing "bus master" bit removed,
- protect bcr2 transition in the same way as longhaul,
- check if Longhaul MSR is present, don't assume that this stepping have this MSR, and other don't,
- voltage scaling added. By default disabled because is untested. Looks like processors on Epia mainboards don't support voltage scaling,
- some FSB scaling compatibility,
- some minor changes.
---
arch/i386/kernel/cpu/cpufreq/Kconfig +1 -1
@@ -202,7 +202,7 @@ config X86_LONGRUN config X86_LONGHAUL tristate "VIA Cyrix III Longhaul" select CPU_FREQ_TABLE - depends on BROKEN + depends on !SMP && !X86_UP_APIC && ACPI_PROCESSOR help This adds the CPUFreq driver for VIA Samuel/CyrixIII, VIA Cyrix Samuel/C3, VIA Cyrix Ezra and VIA Cyrix Ezra-T
arch/i386/kernel/cpu/cpufreq/longhaul.c +289 -341
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arch/i386/kernel/cpu/cpufreq/longhaul.h +51 -346
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Quoted 8 lines · RafaÅ‚ Bilski
Changes in
longhaul.h:
- clock tables merged - differences are little, "longhaul" will do errata for detected CPU,
- eblcr tables merged - reason above,
- format of voltage tables changed,
- added mobile vrm.
Quoted 11 lines
Changes in
longhaul.c:
- most important - now C3 state is causing transition,
- code resopnsible for clearing "bus master" bit removed,
- protect bcr2 transition in the same way as longhaul,
- check if Longhaul MSR is present, don't assume that this stepping have this MSR, and other don't,
- voltage scaling added. By default disabled because is untested. Looks like processors on Epia mainboards don't support voltage scaling,
- some FSB scaling compatibility,
- some minor changes.
Please split this up into easy-to-review single-change-per-diff patchset. This way if it becomes easier to review, and also if there are any objectionable parts, I can drop those whilst still applying the non-contentious parts.
Thanks,
Dave
Signature · 1 line
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