Stop clobbering AMD TSC offsets

This fixes a bug in which HVM VCPUs running on AMD have their TSC offset clobbered (to zero) when they switch to real mode. The consequences of this are nearly unnoticeable in most cases, but the AMD folks (Tom Woller & Travis Betak) agree this is a (minor) bug and have been waiting forever for me to port and post this so they can strike it off their TODO lists.

diff -r c03c4be32469 xen/arch/x86/hvm/svm/svm.c
@@ -2329,9 +2329,6 @@ static int svm_reset_to_realmode(struct 
     /* clear the vmcb and user regs */
     memset(regs, 0, sizeof(struct cpu_user_regs));
    
-    /* VMCB Control */
-    vmcb->tsc_offset = 0;
-
     /* VMCB State */
     vmcb->cr0 = X86_CR0_ET | X86_CR0_PG | X86_CR0_WP;
     v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;

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