DP83848 PHY for AT91RM9200 board

diff -urN --show-c-function u-boot-1.1.4.orig/board/vadatech/dp83848.c u-boot-1.1.4/board/vadatech/dp83848.c
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Sergey Kubushin <[email protected]>: Changed for DP83848 PHY 08/31/2005
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dp83848.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dp84848_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dp83848_IsPhyConnected( AT91PS_EMAC p_mac )
+{
+    unsigned short Id1, Id2;
+
+    at91rm9200_EmacEnableMDIO( p_mac );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_PHYID1_REG, &Id1 );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_PHYID2_REG, &Id2 );
+    at91rm9200_EmacDisableMDIO (p_mac);
+
+    if( (Id1 == DP83848_PHYID1_OUI) && (Id2 == DP83848_PHYID2_OUI) )
+    {
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+/*
+ * Name:
+ *	dp83848_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_GetLinkSpeed( AT91PS_EMAC p_mac )
+{
+    unsigned short stat1, stat2;
+
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_STAT_REG, &stat1 ) )
+    {
+	return FALSE;
+    }
+
+    if( !(stat1 & DP83848_LINK_STATUS) )	/* link status up? */
+    {
+	return FALSE;
+    }
+
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_PHY_STAT_REG, &stat2 ) )
+    {
+	return FALSE;
+    }
+
+    if ( !(stat2 & DP83848_SPEED) && (stat2 & DP83848_DUPLEX) ) 
+    {
+	/*set Emac for 100BaseTX and Full Duplex  */
+	p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if ( (stat2 & DP83848_SPEED) && (stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 10BaseT and Full Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if ( !(stat2 & DP83848_SPEED) && !(stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 100BaseTX and Half Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_SPD;
+	return TRUE;
+    }
+
+     if ( (stat2 & DP83848_SPEED) && !(stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 10BaseT and Half Duplex  */
+	p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dp83848_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_InitPhy( AT91PS_EMAC p_mac )
+{
+    UCHAR ret = TRUE;
+    unsigned short IntValue = 0;
+
+    at91rm9200_EmacEnableMDIO( p_mac );
+
+    if( !dp83848_GetLinkSpeed( p_mac ) ) 
+    {
+	/* Wait and try once more  */
+	udelay(100000);
+        ret = dp83848_GetLinkSpeed(p_mac);
+    }
+
+    /* Disable PHY Interrupts */
+    at91rm9200_EmacWritePhy (p_mac, DP83848_PHY_INTR_CTRL_REG, &IntValue);
+
+    at91rm9200_EmacDisableMDIO( p_mac );
+
+    return( ret );
+}
+
+
+/*
+ * Name:
+ *	dp83848_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_AutoNegotiate( AT91PS_EMAC p_mac, int *status )
+{
+    unsigned short value;
+    unsigned short PhyAnar;
+    unsigned short PhyAnalpar;
+
+    /* Set dp83848 control register */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    value &= ~DP83848_AUTONEG;	/* remove autonegotiation enable */
+    value |= DP83848_ISOLATE;	/* Electrically isolate PHY */
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /* Set the Auto_negotiation Advertisement Register 
+     * MII advertising for Next page, 100BaseTxFD and HD, 
+     * 10BaseTFD and HD, IEEE 802.3 
+     */
+    PhyAnar = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
+	      DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_ANA_REG, &PhyAnar ) )
+    {
+	return FALSE;
+    }
+
+    /* Read the Control Register     */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    value |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /* Restart Auto_negotiation  */
+    value |= DP83848_RESTART_AUTONEG;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /*check AutoNegotiate complete */
+    udelay( 10000 );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_STAT_REG, &value );
+    if( !(value & DP83848_AUTONEG_COMP) )
+    {
+	return FALSE;
+    }
+
+    /* Get the AutoNeg Link partner base page */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_ANLPA_REG, &PhyAnalpar ) )
+    {
+	return FALSE;
+    }
+
+    if( (PhyAnar & DP83848_TX_FDX) && (PhyAnalpar & DP83848_TX_FDX) ) 
+    {
+	/*set MII for 100BaseTX and Full Duplex  */
+	p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if( (PhyAnar & DP83848_10_FDX) && (PhyAnalpar & DP83848_10_FDX) ) 
+    {
+	/*set MII for 10BaseT and Full Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface( AT91PS_PhyOps p_phyops )
+{
+    p_phyops->Init           = dp83848_InitPhy;
+    p_phyops->IsPhyConnected = dp83848_IsPhyConnected;
+    p_phyops->GetLinkSpeed   = dp83848_GetLinkSpeed;
+    p_phyops->AutoNegotiate  = dp83848_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */

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