MIPS question
For those who know a little about U-Boot on MIPS:
in include/asm-mips/addrspace.h line 52, there is a
#define UNCACHED_SDRAM(a) PHYSADDR(a)
The question is: shouldn't we use KSEG1ADDR() instead of PHYSADDR()? If not, this means we have to actually map KUSEG ?
Vlad
Quoted 5 lines · Vlad Lungu
in
include/asm-mips/addrspace.hline 52, there is a#define
UNCACHED_SDRAM(a)PHYSADDR(a)The question is: shouldn't we use
KSEG1ADDR()instead ofPHYSADDR()?
I think we should. At least my target boards need that change.
http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921
note: Wrt dcache_disable() part, please take into account
Stefan's comment.
Anyway I seriously wonder whether other mips ports work as it is.
thanks,
Shinya
Quoted 4 lines · Shinya Kuribayashi
Quoted 2 lines · Vlad Lungu
in
include/asm-mips/addrspace.hline 52, there is a
Quoted 9 lines
Quoted 4 lines
#define
UNCACHED_SDRAM(a)PHYSADDR(a)The question is: shouldn't we use
KSEG1ADDR()instead ofPHYSADDR()?I think we should. At least my target boards need that change.
http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921
And what board would that be? Or it's not in the tree?
Quoted 6 lines
note: Wrt
dcache_disable()part, please take into account
Stefan's comment.Anyway I seriously wonder whether other mips ports work as it is.
<comment mode="AOL"> me too </comment>
The RAM might be mapped at 0 too on some boards, that's why it works with PHYSADDR(). Or people are simply bootelf-ing Linux, that's why the bug was not catched before (I think the only use of that macro is in lib_mips/mips_linux.c i.e. bootm). Note that the Au1x00 boards ( and another one, can't remember the name) do 0x20000000|a or something like that, which when you go from KSEG0 (0x8???????) produces 0xa???????, an address in KSEG1.
Wolfgang, should I submit a patch on this for 1.3.0?
Vlad
Quoted 10 lines · Vlad Lungu
Quoted 9 lines · Shinya Kuribayashi
Quoted 6 lines · Vlad Lungu
in
include/asm-mips/addrspace.hline 52, there is a#define
UNCACHED_SDRAM(a)PHYSADDR(a)The question is: shouldn't we use
KSEG1ADDR()instead ofPHYSADDR()?
Quoted 6 lines
Quoted 5 lines
I think we should. At least my target boards need that change.
http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921
And what board would that be? Or it's not in the tree?
It's NEC mips custom board, and is not (will not be) in upstream. These are VRcore-based or MIPScore-based, not Au1XXX-based.
Quoted 10 lines
Quoted 6 lines
note: Wrt
dcache_disable()part, please take into account
Stefan's comment.Anyway I seriously wonder whether other mips ports work as it is.
<comment mode="AOL"> me too </comment>
The RAM might be mapped at 0 too on some boards, that's why it works with
PHYSADDR(). Or people are
Hmm.. our board has system RAM physically mapped at zero, but never works with PHYSADDR(). If TLB uninitialized, we encounter tlb address error on 0x0 access. Am I miss something?
Quoted 2 lines
simply bootelf-ing Linux, that's why the bug was not catched before (I think the only use of that macro is in
lib_mips/mips_linux.ci.e.
Agreed.
Quoted 4 lines
bootm). Note that the Au1x00 boards ( and another one, can't remember the name) do 0x20000000|a or something like that, which when you go from KSEG0 (
0x8???????)
produces0xa???????, an address in KSEG1.
True, I think UNCACHED_SDRAM() works only with au1xxx for now.
Quoted 1 line
Wolfgang, should I submit a patch on this for 1.3.0?
Feel free to add my signed-off-by:
thanks,
Shinya