Fixed mips_io_port_base build errors.
PATCH 1/1 Fixed mips_io_port_base build errors.
From: Shinya Kuribayashi <[email protected]>
This patch has been sent on:
- 29 Sep 2007
Although mips_io_port_base is currently a part of IDE command, it is quite fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move it to MIPS general part, and introduce `set_io_port_base()' from Linux.
This patch is triggered by multiple definition of `mips_io_port_base' build error on gth2 (and tb0229 also needs this fix.)
board/gth2/libgth2.a(gth2.o): In function `log_serial_char':/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1
Signed-off-by Shinya Kuribayashi <[email protected]>
---
board/dbau1x00/dbau1x00.c | 4 ++++ board/gth2/gth2.c | 6 ++++-- board/incaip/incaip.c | 5 +++-- board/pb1x00/pb1x00.c | 4 ++++ board/purple/purple.c | 3 +++ board/tb0229/tb0229.c | 7 +++---- common/cmd_ide.c | 4 ---- include/asm-mips/io.h | 16 +++++++++++++++- lib_mips/board.c | 5 +++++ 9 files changed, 41 insertions(+), 13 deletions(-)
board/dbau1x00/dbau1x00.c +4 -0
@@ -25,6 +25,7 @@#include <command.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> +#include <asm/io.h> long int initdram (int board_type) {
@@ -77,6 +78,9 @@ int checkboard (void)default :printf ("Unsupported cpu %d, proc_id=0x%x\n" , proc_id >>24 , proc_id); } + +set_io_port_base (0 ); +#ifdef CONFIG_IDE_PCMCIA /* Enable 3.3 V on slot 0 ( VCC ) No 5V */
board/gth2/gth2.c +4 -2
@@ -26,14 +26,13 @@#include <asm/au1x00.h> #include <asm/addrspace.h> #include <asm/mipsregs.h> +#include <asm/io.h> #include <watchdog.h> #include "ee_access.h" static int wdi_status =0 ; -unsigned long mips_io_port_base =0 ; -#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
@@ -147,6 +146,9 @@ int checkboard (void)default :printf ("Unsupported cpu %d, proc_id=0x%x\n" , proc_id >>24 , proc_id); } + +set_io_port_base (0 ); +#ifdef CONFIG_IDE_PCMCIA /* PCMCIA is on a 36 bit physical address. We need to map it into a 32 bit addresses */
board/incaip/incaip.c +3 -2
@@ -25,7 +25,7 @@#include <command.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> - +#include <asm/io.h> extern uint incaip_get_cpuclk (void );
@@ -85,7 +85,6 @@ long int initdram(int board_type)int checkboard (void ) { -unsigned long chipid = *INCA_IP_WDT_CHIPID ;int part_num;
@@ -107,5 +106,7 @@ int checkboard (void)printf ("CPU Speed %d MHz\n" ,incaip_get_cpuclk ()/1000000 ); +set_io_port_base (0 ); +return 0 ; }
board/pb1x00/pb1x00.c +4 -0
@@ -25,6 +25,7 @@#include <command.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> +#include <asm/io.h> long int initdram (int board_type) {
@@ -69,6 +70,9 @@ int checkboard (void)default :printf ("Unsupported cpu %d, proc_id=0x%x\n" , proc_id >>24 , proc_id); } + +set_io_port_base (0 ); +#if defined(CONFIG_IDE_PCMCIA ) &&0 /* Enable 3.3 V on slot 0 ( VCC ) No 5V */
board/purple/purple.c +3 -0
@@ -26,6 +26,7 @@#include <asm/inca-ip.h> #include <asm/regdef.h> #include <asm/mipsregs.h> +#include <asm/io.h> #include <asm/addrspace.h> #include <asm/cacheops.h>
@@ -145,6 +146,8 @@ int checkboard (void)printf ("CPU Speed %d MHz\n" ,CPU_CLOCK_RATE /1000000 ); +set_io_port_base (0 ); +return 0 ; }
board/tb0229/tb0229.c +3 -4
@@ -13,10 +13,9 @@#include <command.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> +#include <asm/io.h> #include <pci.h> -unsigned long mips_io_port_base =0 ; -#if defined(CONFIG_PCI )static struct pci_controller hose;
@@ -26,17 +25,17 @@ void pci_init_board (void) }#endif -long int initdram (int board_type) {return get_ram_size (CFG_SDRAM_BASE ,0x8000000 ); } -int checkboard (void ) {printf ("Board: TANBAC TB0229 " );printf ("(CPU Speed %d MHz)\n" , (int )CPU_CLOCK_RATE /1000000 ); +set_io_port_base (0 ); +return 0 ; }
common/cmd_ide.c +0 -4
@@ -54,10 +54,6 @@#ifndef __PPC__#include <asm/io.h> -#ifdef __MIPS__ -/* Macros depend on this variable */ -unsigned long mips_io_port_base =0 ; -#endif #endif #ifdef CONFIG_IDE_8xx_DIRECT
include/asm-mips/io.h +15 -1
@@ -71,7 +71,21 @@* instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* +* Gcc will generate code to load the value of mips_io_port_base after each +* function call which may be fairly wasteful in some cases. So we don't +* play quite by the book. We tell gcc mips_io_port_base is a long variable +* which solves the code generation issue. Now we need to violate the +* aliasing rules a little to make initialization possible and finally we +* will need the barrier() to fight side effects of the aliasing chat. +* This trickery will eventually collapse under gcc's optimizer. Oh well. +*/ +static inline void set_io_port_base (unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +}/* * Thanks to James van Artsdalen for a better timing-fix than
lib_mips/board.c +5 -0
@@ -62,6 +62,11 @@ static ulong mem_malloc_start;static ulong mem_malloc_end;static ulong mem_malloc_brk; +/* +* mips_io_port_base is the begin of the address space to which x86 style +* I/O ports are mapped. +*/ +unsigned long mips_io_port_base =-1 ;/* * The Malloc area is immediately below the monitor copy in DRAM