PPC4xx: Cosmetic changes
PATCH 1/2 PPC4xx: Cosmetic changes
Signed-off-by Larry Johnson <[email protected]>
---
cpu/ppc4xx/miiphy.c | 58 +++++++--------------
cpu/ppc4xx/miiphy.c +20 -38
@@ -27,19 +27,6 @@| | Author: Mark Wisner | -| Change Activity- -| -| Date Description of Change BY -| --------- --------------------- --- -| 05-May-99 Created MKW -| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to -| better match OPB speed. Also modified delay times. JWB -| 29-Jul-99 Added Full duplex support MKW -| 24-Aug-99 Removed printf from dp83843_duplex() JWB -| 19-Jul-00 Ported to esd cpci405 sr -| 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS -| <[email protected]> -| +-----------------------------------------------------------------------------*/ #include <common.h>
@@ -60,7 +47,6 @@ void miiphy_dump (char *devname, unsigned char addr)unsigned long i;unsigned short data; -for (i =0 ; i <0x1A ; i++) {if (miiphy_read (devname, addr, i, &data)) {printf ("read error for reg %lx\n" , i);
@@ -75,7 +61,6 @@ void miiphy_dump (char *devname, unsigned char addr) }/* end for loop */ }/* end dump */ -/***********************************************************/ /* (Re)start autonegotiation */ /***********************************************************/
@@ -102,7 +87,6 @@ int phy_setup_aneg (char *devname, unsigned char addr)return 0 ; } -/***********************************************************/ /* read a phy reg and return the value with a rc */ /***********************************************************/
@@ -145,21 +129,20 @@ unsigned int miiphy_getemac_offset (void)#endif } - -int emac4xx_miiphy_read (char *devname,unsigned char addr, -unsigned char reg,unsigned short *value) +int emac4xx_miiphy_read (char *devname,unsigned char addr,unsigned char reg, +unsigned short *value) {unsigned long sta_reg;/* STA scratch area */ unsigned long i;unsigned long emac_reg; - emac_reg =miiphy_getemac_offset ();/* see if it is ready for 1000 nsec */ i =0 ;/* see if it is ready for sec */ -while ((in32 (EMAC_STACR + emac_reg) &EMAC_STACR_OC ) ==EMAC_STACR_OC_MASK ) { +while ((in32 (EMAC_STACR + emac_reg) &EMAC_STACR_OC ) == +EMAC_STACR_OC_MASK ) {udelay (7 );if (i >5 ) {#ifdef ET_DEBUG
@@ -175,10 +158,10 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,/* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX ) || defined(CONFIG_440SPE ) || \ defined(CONFIG_440EPX ) || defined(CONFIG_440GRX ) -#if defined(CONFIG_IBM_EMAC4_V4 )/* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK ) |EMAC_STACR_READ ; +#if defined(CONFIG_IBM_EMAC4_V4 )/* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK ) |EMAC_STACR_READ ;#else - sta_reg |=EMAC_STACR_READ ; + sta_reg |=EMAC_STACR_READ ;#endif #else sta_reg = (sta_reg |EMAC_STACR_READ ) & ~EMAC_STACR_CLK_100MHZ ;
@@ -198,7 +181,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg =in32 (EMAC_STACR + emac_reg);#ifdef ET_DEBUG -printf ("a21: read : EMAC_STACR=0x%0x\n" , sta_reg);/* test-only */ +printf ("a21: read : EMAC_STACR=0x%0x\n" , sta_reg);/* test-only */ #endif i =0 ;while ((sta_reg &EMAC_STACR_OC ) ==EMAC_STACR_OC_MASK ) {
@@ -216,19 +199,17 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,return -1 ; } - *value = *(short *) (&sta_reg); + *value = *(short *)(&sta_reg);return 0 ; - }/* phy_read */ -/***********************************************************/ /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (char *devname,unsigned char addr, -unsigned char reg,unsigned short value) +int emac4xx_miiphy_write (char *devname,unsigned char addr,unsigned char reg, +unsigned short value) {unsigned long sta_reg;/* STA scratch area */ unsigned long i;
@@ -238,7 +219,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,/* see if it is ready for 1000 nsec */ i =0 ; -while ((in32 (EMAC_STACR + emac_reg) &EMAC_STACR_OC ) ==EMAC_STACR_OC_MASK ) { +while ((in32 (EMAC_STACR + emac_reg) &EMAC_STACR_OC ) == +EMAC_STACR_OC_MASK ) {if (i >5 )return -1 ;udelay (7 );
@@ -249,10 +231,10 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,/* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX ) || defined(CONFIG_440SPE ) || \ defined(CONFIG_440EPX ) || defined(CONFIG_440GRX ) -#if defined(CONFIG_IBM_EMAC4_V4 )/* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK ) |EMAC_STACR_WRITE ; +#if defined(CONFIG_IBM_EMAC4_V4 )/* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK ) |EMAC_STACR_WRITE ;#else - sta_reg |=EMAC_STACR_WRITE ; + sta_reg |=EMAC_STACR_WRITE ;#endif #else sta_reg = (sta_reg |EMAC_STACR_WRITE ) & ~EMAC_STACR_CLK_100MHZ ;
@@ -263,8 +245,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, !defined (CONFIG_440EPX ) && !defined (CONFIG_440GRX ) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */#endif - sta_reg = sta_reg | ((unsigned long ) addr <<5 );/* Phy address */ - sta_reg = sta_reg |EMAC_STACR_OC_MASK ;/* new IBM emac v4 */ + sta_reg = sta_reg | ((unsigned long )addr <<5 );/* Phy address */ + sta_reg = sta_reg |EMAC_STACR_OC_MASK ;/* new IBM emac v4 */ memcpy (&sta_reg, &value,2 );/* put in data */ out32 (EMAC_STACR + emac_reg, sta_reg);
@@ -273,7 +255,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, i =0 ; sta_reg =in32 (EMAC_STACR + emac_reg);#ifdef ET_DEBUG -printf ("a31: read : EMAC_STACR=0x%0x\n" , sta_reg);/* test-only */ +printf ("a31: read : EMAC_STACR=0x%0x\n" , sta_reg);/* test-only */ #endif while ((sta_reg &EMAC_STACR_OC ) ==EMAC_STACR_OC_MASK ) {udelay (7 );
@@ -290,4 +272,4 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,return -1 ;return 0 ; -}/* phy_write */ +}/* phy_write */