Problem with cache diag on sequoia board in PPC4xx branch for-1.3.2

Hi Stefan,

In testing my merge of Korat PPC440EPx board support into PPC4xx branch "for-1.3.2", I found problem with the "DIAG RUN CACHE" command. The same problem occurs in the latest for-1.3.2 code for sequoia. Here is a copy of the console output showing what happens:

=> diag run cache
Bad trap at PC: ff70220, SR: 21000, vector=1300
NIP: 0FF70220 XER: 2000005F LR: 0FF702D4 REGS: 0ff17870 TRAP: 1300 DEAR: 10000000
MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 0000003F 0FF17960 7FFFFFFF 10000000 00000400 00000400 00000020 FFFFFFFF
GPR08: 0FFFBFEC 0FF6F888 0000000C 10000000 00000400 00000000 0FFABD00 0FFBA000
GPR16: 15809012 22406001 C1904012 0FF17B6A 00000001 00000000 0FF17C65 00000000
GPR24: 00000600 0000000C 00000000 00000001 0FFA6AE8 0FF17F34 0FFAC714 0FF6F7DC Call backtrace:
0FF17A44 0FF6B0E8 0FF6B4AC 0FF734D0 0FF71270 0FF71450 0FF5ECA4 0FF5C6B8 F1FFFFFF
Exception

U-Boot 1.3.1-g76ace773 (Dec 20 2007 - 17:07:17)

CPU: AMCC PowerPC 440EPx Rev. A at 528 MHz (PLB=132, OPB=66, EBC=66 MHz)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache

Board: Sequoia - AMCC PPC440EPx Evaluation Board, Rev. F, PCI=33 MHz, serial# 52149
I2C:   ready
DTT:   1 is 24 C
DRAM:  256 MB
FLASH: 64 MB
NAND:  32 MiB
PCI:   Bus Dev VenId DevId Class Int
In:    serial
Out:   serial
Err:   serial
USB:   Host(int phy) Device(ext phy)
Net:   ppc_4xx_eth0, ppc_4xx_eth1

Type "run flash_nfs" to mount root filesystem over NFS

=>

This problem does not occur on sequoia using the latest mainline (i.e., master branch) code from the PPC4xx repository.

Just thought you'd like to know. :-)

Best regards,
Larry

Hi Larry,

Thanks for reporting. I'll try to take a look at it in the next days. But I have no problems at all, if you provide a patch to fix it. ;)

Best regards,
Stefan

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OK, I found the problem and fixed in the for-1.3.2 branch:

commit 8092791c5d959e89f9bc4ed0ff880c3509da743f

Author: Stefan Roese <[email protected]>
Date:   Sat Dec 22 12:18:26 2007 +0100

ppc4xx: Fix problem in 44x cache POST routine

As repoted by Larry Johnson, running "diag run cache" caused a crash in U-Boot. This problem was introduced by a patch that removed the TLB entry for the cache test after the test has completed. Since this TLB was only setup once, a 2nd attempt to run this cache test failed with a crash. Now this TLB entry is created every time the routine is called.

index 30d5088..c8ddf35 100644
@@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
 int cache_post_test5 (int tlb, void *p, int size);
 int cache_post_test6 (int tlb, void *p, int size);
 
-static int tlb = -1;           /* index to the victim TLB entry */
-
 #ifdef CONFIG_440
 static unsigned char testarea[CACHE_POST_SIZE]
 __attribute__((__aligned__(CACHE_POST_SIZE)));

@@ -60,7 +58,7 @@ __attribute__((__aligned__(CACHE_POST_SIZE)));
 
 int cache_post_test (int flags)
 {
-       void* virt = (void*)CFG_POST_CACHE_ADDR;
+       void *virt = (void *)CFG_POST_CACHE_ADDR;
        int ints;
        int res = 0;
 

@@ -72,26 +70,25 @@ int cache_post_test (int flags)
         */
 #ifdef CONFIG_440
        int word0, i;
+       int tlb;                /* index to the victim TLB entry */
 
-       if (tlb < 0) {
-               /*
-                * Allocate a new TLB entry, since we are going to modify
-                * the write-through and caching inhibited storage attributes.
-                */
-               program_tlb((u32)testarea, (u32)virt,
-                           CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
-
-               /* Find the TLB entry */
-               for (i = 0;; i++) {
-                       if (i >= PPC4XX_TLB_SIZE) {
-                               printf ("Failed to program tlb entry\n");
-                               return -1;
-                       }
-                       word0 = mftlb1(i);
-                       if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
-                               tlb = i;
-                               break;
-                       }
+       /*
+        * Allocate a new TLB entry, since we are going to modify
+        * the write-through and caching inhibited storage attributes.
+        */
+       program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
+                   TLB_WORD2_I_ENABLE);
+
+       /* Find the TLB entry */
+       for (i = 0;; i++) {
+               if (i >= PPC4XX_TLB_SIZE) {
+                       printf ("Failed to program tlb entry\n");
+                       return -1;
+               }
+               word0 = mftlb1(i);
+               if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+                       tlb = i;
+                       break;
                }
        }
 #endif

This fixes the problem on Korat as well. Thanks!

Best regards,
Larry