CoreDUO CPU

PATCH In review Alexander Graf 2 participants 4 messages Jan 8, 2008 – Jan 14, 2008

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Alexander Graf

author

2008-01-08 15:11 UTC #0 lore raw

PATCH 5/9 CoreDUO CPU

Mac OS X as is has a condition to only run on family 13 Intel CPUs, so this adds a definition for a CoreDuo CPU.
Furthermore it adds the MSR Mac OS X uses to read the CPU multiplier and the CPUID used to read the cache information.

target-i386/cpu.h +2 -0

Index: qemu-snapshot-2008-01-08_05/target-i386/cpu.h
===================================================================
@@ -232,6 +232,8 @@
 #define MSR_MCG_STATUS                  0x17a
 #define MSR_MCG_CTL                     0x17b
 
+#define MSR_IA32_PERF_STS               0x198
+
 #define MSR_PAT                         0x277
 
 #define MSR_EFER                        0xc0000080

target-i386/helper.c +77 -0

89 lines not on this page · raw message

target-i386/helper2.c +17 -0

Index: qemu-snapshot-2008-01-08_05/target-i386/helper2.c
===================================================================
@@ -156,6 +156,23 @@ static x86_def_t x86_defs[] = {
     },
 #endif
     {
+        .name = "coreduo",
+        .level = 3,
+        .vendor1 = 0x756e6547, /* "Genu" */
+        .vendor2 = 0x49656e69, /* "ineI" */
+        .vendor3 = 0x6c65746e, /* "ntel" */
+        .family = 6,
+        .model = 13,
+        .stepping = 1,
+        .features = PPRO_FEATURES | 
+            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+            CPUID_PSE36,
+        .ext_features = CPUID_EXT_SSE3,
+        .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | 
+             CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+        .xlevel = 0x8000000A,
+    },
+    {
         .name = "qemu32",
         .level = 2,
         .family = 6,

Dan Kenigsberg

2008-01-11 10:47 UTC #1 lore raw

Quoted 74 lines · Alexander Graf

Index: qemu-snapshot-2008-01-08_05/target-i386/cpu.h
===================================================================

target-i386/cpu.h +2 -0

@@ -232,6 +232,8 @@
 #define MSR_MCG_STATUS                  0x17a
 #define MSR_MCG_CTL                     0x17b
 
+#define MSR_IA32_PERF_STS               0x198
+
 #define MSR_PAT                         0x277
 
 #define MSR_EFER                        0xc0000080

Index: qemu-snapshot-2008-01-08_05/target-i386/helper.c
===================================================================

target-i386/helper.c +48 -0

@@ -1710,6 +1710,79 @@ void helper_cpuid(void)
         ECX = 0;
         EDX = 0x2c307d;
         break;
+    case 4:
+        /* cache info: needed for Core Duo compatibility */
+/* From the Intel documentation:
+EAX: 
+ Bits 4-0: Cache Type** 
+ Bits 7-5: Cache Level (starts at 1) 
+ Bits 8: Self Initializing cache level (does not need SW initialization)
+ Bits 9: Fully Associative cache Bits
+  13-10: Reserved Bits 
+  25-14: Number of threads sharing this cache* Bits
+  31-26: Number of processor cores on this die (Multicore)*
+EBX:
+ Bits 11-0: L = System Coherency Line Size*
+ Bits 21-12: P = Physical Line partitions*
+ Bits 31-22: W = Ways of associativity*
+ECX:
+ Bits 31-0: S = Number of Sets*
+EDX: Reserved
+ * Add one to the value in the register file to get the number. For example, the number
+   of processor cores is EAX[31:26]+1.
+** Cache Types fields
+     0 = Null - No more caches
+     1 = Data Cache
+     2 = Instruction Cache
+     3 = Unified Cache
+  31-4 = Reserved
+*/
+
+        switch (ECX) {
+            case 0: // L1 cache info
+/*                EAX = 3            // Unified Cache 
+                    | (1 << 5)     // L1 Cache
+                    | (1 << 8);    // Self Initializing
+                EBX = 63           // Line size = 64 bytes
+                    | (1022 << 12) // Partitions = 1024 bytes
+                    | (0 << 22);   // Ways = 2
+                ECX = 0x3f;           // One L1 Cache
+                EDX = 0;*/
+                EAX = 0x0000123;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;
+            case 1: // L2 cache info
+/*                EAX = 3            // Unified Cache 
+                    | (2 << 5)     // L2 Cache
+                    | (1 << 8);    // Self Initializing
+                EBX = 63           // Line size = 64 bytes

target-i386/helper.c void helper_cpuid(void) · line 1770

Quoted 10 lines

target-i386/helper.c +10 -0

+                    | (1023 << 12) // Partitions = 1024 bytes
+                    | (0 << 22);   // Ways = 512
+                ECX = 0;           // One L2 Cache
+                EDX = 0;
+*/
+                EAX = 0x0000122;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;

Why do you explain one set of values, and actually use something different? It confuses the untrained reader (me).

Dan.

Alexander Graf

author

2008-01-11 12:24 UTC #2 lore raw

Quoted 91 lines · Dan Kenigsberg

Quoted 76 lines · Alexander Graf

Index: qemu-snapshot-2008-01-08_05/target-i386/cpu.h
===================================================================

target-i386/cpu.h +2 -0

@@ -232,6 +232,8 @@
 #define MSR_MCG_STATUS                  0x17a
 #define MSR_MCG_CTL                     0x17b
 
+#define MSR_IA32_PERF_STS               0x198
+
 #define MSR_PAT                         0x277
 
 #define MSR_EFER                        0xc0000080

Index: qemu-snapshot-2008-01-08_05/target-i386/helper.c
===================================================================

target-i386/helper.c +19 -0

@@ -1710,6 +1710,79 @@ void helper_cpuid(void)
        ECX = 0;
        EDX = 0x2c307d;
        break;
+    case 4:
+        /* cache info: needed for Core Duo compatibility */
+/* From the Intel documentation:
+EAX:
+ Bits 4-0: Cache Type**
+ Bits 7-5: Cache Level (starts at 1)
+ Bits 8: Self Initializing cache level (does not need SW  
 initialization)
+ Bits 9: Fully Associative cache Bits
+  13-10: Reserved Bits
+  25-14: Number of threads sharing this cache* Bits
+  31-26: Number of processor cores on this die (Multicore)*
+EBX:
+ Bits 11-0: L = System Coherency Line Size*
+ Bits 21-12: P = Physical Line partitions*
+ Bits 31-22: W = Ways of associativity*
+ECX:
+ Bits 31-0: S = Number of Sets*
+EDX: Reserved
+ * Add one to the value in the register file to get the number.

For example, the number

target-i386/helper.c +29 -0

+   of processor cores is EAX[31:26]+1.
+** Cache Types fields
+     0 = Null - No more caches
+     1 = Data Cache
+     2 = Instruction Cache
+     3 = Unified Cache
+  31-4 = Reserved
+*/
+
+        switch (ECX) {
+            case 0: // L1 cache info
+/*                EAX = 3            // Unified Cache
+                    | (1 << 5)     // L1 Cache
+                    | (1 << 8);    // Self Initializing
+                EBX = 63           // Line size = 64 bytes
+                    | (1022 << 12) // Partitions = 1024 bytes
+                    | (0 << 22);   // Ways = 2
+                ECX = 0x3f;           // One L1 Cache
+                EDX = 0;*/
+                EAX = 0x0000123;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;
+            case 1: // L2 cache info
+/*                EAX = 3            // Unified Cache
+                    | (2 << 5)     // L2 Cache
+                    | (1 << 8);    // Self Initializing
+                EBX = 63           // Line size = 64 bytes

target-i386/helper.c void helper_cpuid(void) · line 1770

Quoted 10 lines

target-i386/helper.c +10 -0

+                    | (1023 << 12) // Partitions = 1024 bytes
+                    | (0 << 22);   // Ways = 512
+                ECX = 0;           // One L2 Cache
+                EDX = 0;
+*/
+                EAX = 0x0000122;
+                EBX = 0x1c0003f;
+                ECX = 0x000003f;
+                EDX = 0x0000001;
+                break;

Why do you explain one set of values, and actually use something different? It confuses the untrained reader (me).

Quoted 3 lines

Dan.

Basically because I created the values dynamically at first, which broke at some point. So I just read the real values that a real CPU gives and put them in instead.

Yes, I should have dropped the commented-out values. Please remove them when merging.

Alex

Alexander Graf

author

2008-01-14 13:36 UTC #3 lore raw

In reply to Alexander Graf

Quoted 5 lines · Alexander Graf

Mac OS X as is has a condition to only run on family 13 Intel CPUs, so this adds a definition for a CoreDuo CPU.
Furthermore it adds the MSR Mac OS X uses to read the CPU multiplier and the CPUID used to read the cache information.

This is an updates version of the very same patch. Compared to the previous version,
it fixes the cpuid-level and the cache information, making system_profiler work on Mac OS X.

Regards,

Alex

target-i386/cpu.h +2 -0

Index: qemu-snapshot-2008-01-08_05/target-i386/cpu.h
===================================================================
@@ -232,6 +232,8 @@
 #define MSR_MCG_STATUS                  0x17a
 #define MSR_MCG_CTL                     0x17b
 
+#define MSR_IA32_PERF_STS               0x198
+
 #define MSR_PAT                         0x277
 
 #define MSR_EFER                        0xc0000080

target-i386/helper.c +60 -0

72 lines not on this page · raw message

target-i386/helper2.c +17 -0

Index: qemu-snapshot-2008-01-08_05/target-i386/helper2.c
===================================================================
@@ -156,6 +156,23 @@ static x86_def_t x86_defs[] = {
     },
 #endif
     {
+        .name = "coreduo",
+        .level = 4,
+        .vendor1 = 0x756e6547, /* "Genu" */
+        .vendor2 = 0x49656e69, /* "ineI" */
+        .vendor3 = 0x6c65746e, /* "ntel" */
+        .family = 6,
+        .model = 14,
+        .stepping = 1,
+        .features = PPRO_FEATURES | 
+            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+            CPUID_PSE36,
+        .ext_features = CPUID_EXT_SSE3,
+        .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | 
+             CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+        .xlevel = 0x8000000A,
+    },
+    {
         .name = "qemu32",
         .level = 2,
         .family = 6,