NAND hardware ECC controller on at91sam9263 / at91sam9260

index 105f840..f494d92 100644
@@ -288,11 +288,16 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE	AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-	{
+	[0] = {
 		.start	= NAND_BASE,
 		.end	= NAND_BASE + SZ_256M - 1,
 		.flags	= IORESOURCE_MEM,
-	}
+	},
+	[1] = {
+		.start	= AT91SAM9260_ECC,
+		.end	= AT91SAM9260_ECC + SZ_512 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
 };
 
 static struct platform_device at91sam9260_nand_device = {

index 0b12e1a..fc0d50a 100644
@@ -358,11 +358,16 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE	AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-	{
+	[0] = {
 		.start	= NAND_BASE,
 		.end	= NAND_BASE + SZ_256M - 1,
 		.flags	= IORESOURCE_MEM,
-	}
+	},
+	[1] = {
+		.start	= AT91SAM9263_ECC0,
+		.end	= AT91SAM9263_ECC0 + SZ_512 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
 };
 
 static struct platform_device at91sam9263_nand_device = {

433 lines not on this page · raw message

index ff93df5..0dc4e6b 100644
@@ -13,26 +13,28 @@
 #ifndef AT91_ECC_H
 #define AT91_ECC_H
 
-#define AT91_ECC_CR		(AT91_ECC + 0x00)	/* Control register */
+/* ECC registers offsets */
+#define AT91_ECC_CR		0x00				/* Control register */
 #define		AT91_ECC_RST		(1 << 0)		/* Reset parity */
 
-#define AT91_ECC_MR		(AT91_ECC + 0x04)	/* Mode register */
+#define AT91_ECC_MR		0x04				/* Mode register */
 #define		AT91_ECC_PAGESIZE	(3 << 0)		/* Page Size */
 #define			AT91_ECC_PAGESIZE_528		(0)
 #define			AT91_ECC_PAGESIZE_1056		(1)
 #define			AT91_ECC_PAGESIZE_2112		(2)
 #define			AT91_ECC_PAGESIZE_4224		(3)
 
-#define AT91_ECC_SR		(AT91_ECC + 0x08)	/* Status register */
+#define AT91_ECC_SR		0x08				/* Status register */
 #define		AT91_ECC_RECERR		(1 << 0)		/* Recoverable Error */
 #define		AT91_ECC_ECCERR		(1 << 1)		/* ECC Single Bit Error */
 #define		AT91_ECC_MULERR		(1 << 2)		/* Multiple Errors */
 
-#define AT91_ECC_PR		(AT91_ECC + 0x0c)	/* Parity register */
+#define AT91_ECC_PR		0x0c				/* Parity register */
 #define		AT91_ECC_BITADDR	(0xf << 0)		/* Bit Error Address */
 #define		AT91_ECC_WORDADDR	(0xfff << 4)		/* Word Error Address */
+#define		AT91_ECC_PARITY		(0xffff << 0)		/* Parity */
 
-#define AT91_ECC_NPR		(AT91_ECC + 0x10)	/* NParity register */
+#define AT91_ECC_NPR		0x10				/* NParity register */
 #define		AT91_ECC_NPARITY	(0xffff << 0)		/* NParity */
 
 #endif

index c8934fe..b2be92b 100644
@@ -79,6 +79,27 @@
 #define AT91_BASE_SYS			0xffffe800
 
 /*
+ * System Peripherals physical base addresses.
+ */
+#define AT91SAM9260_ECC		0xffffe800
+#define AT91SAM9260_SDRAMC	0xffffea00
+#define AT91SAM9260_SMC		0xffffec00
+#define AT91SAM9260_MATRIX	0xffffee00
+#define AT91SAM9260_CCFG	0xffffef10
+#define AT91SAM9260_AIC		0xfffff000
+#define AT91SAM9260_DBGU	0xfffff200
+#define AT91SAM9260_PIOA	0xfffff400
+#define AT91SAM9260_PIOB	0xfffff600
+#define AT91SAM9260_PIOC	0xfffff800
+#define AT91SAM9260_PMC		0xfffffc00
+#define AT91SAM9260_RSTC	0xfffffd00
+#define AT91SAM9260_SHDWC	0xfffffd10
+#define AT91SAM9260_RTT		0xfffffd20
+#define AT91SAM9260_PIT		0xfffffd30
+#define AT91SAM9260_WDT		0xfffffd40
+#define AT91SAM9260_GPBR	0xfffffd50
+
+/*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)

index 018a647..acf6bb1 100644
@@ -75,6 +75,33 @@
 #define AT91_BASE_SYS			0xffffe000
 
 /*
+ * System Peripherals physical base addresses.
+ */
+#define AT91SAM9263_ECC0	0xffffe000
+#define AT91SAM9263_SDRAMC0	0xffffe200
+#define AT91SAM9263_SMC0	0xffffe400
+#define AT91SAM9263_ECC1	0xffffe600
+#define AT91SAM9263_SDRAMC1	0xffffe800
+#define AT91SAM9263_SMC1	0xffffea00
+#define AT91SAM9263_MATRIX	0xffffec00
+#define AT91SAM9263_CCFG	0xffffed10
+#define AT91SAM9263_DBGU	0xffffee00
+#define AT91SAM9263_AIC		0xfffff000
+#define AT91SAM9263_PIOA	0xfffff200
+#define AT91SAM9263_PIOB	0xfffff400
+#define AT91SAM9263_PIOC	0xfffff600
+#define AT91SAM9263_PIOD	0xfffff800
+#define AT91SAM9263_PIOE	0xfffffa00
+#define AT91SAM9263_PMC		0xfffffc00
+#define AT91SAM9263_RSTC	0xfffffd00
+#define AT91SAM9263_SHDWC	0xfffffd10
+#define AT91SAM9263_RTT0	0xfffffd20
+#define AT91SAM9263_PIT		0xfffffd30
+#define AT91SAM9263_WDT		0xfffffd40
+#define AT91SAM9263_RTT1	0xfffffd50
+#define AT91SAM9263_GPBR	0xfffffd60
+
+/*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC0	(0xffffe000 - AT91_BASE_SYS)

434 lines not on this page · raw message

@@ -199,7 +199,7 @@ static int at91_nand_calculate(struct mt
 	unsigned int ecc_value;
 
 	/* get the first 2 ECC bytes */
-	ecc_value = ecc_readl(host->ecc, PR) & AT91_ECC_PARITY;
+	ecc_value = ecc_readl(host->ecc, PR);
 
 	ecc_code[eccpos[0]] = ecc_value & 0xFF;
 	ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;