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Implement flush_cache()

U-Boot-Users Shinya Kuribayashi 2 participants 4 messages Mar 18, 2008 – Mar 23, 2008

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Shinya Kuribayashi

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#0 lore raw
Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cpu.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)
cpu/mips/cpu.c +21 -0
index 7559ac6..71e5028 100644
@@ -25,6 +25,17 @@
 #include <command.h>
 #include <asm/inca-ip.h>
 #include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+
+#define cache_op(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	cache	%0, %1					\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {

@@ -41,6 +52,16 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
+	unsigned long lsize = CFG_DCACHE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, start_addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
 }
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
#1 lore raw
Quoted 8 lines · Shinya Kuribayashi
Signed-off-by Shinya Kuribayashi <[email protected]>

---
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, start_addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }

looking at how cache_flush() is used (see common/cmd_load.c, common/cmd_elf.c, etc), I believe this loop should also do a cache_op with Hit_Invalidate_I to invalidate the icache.

seems like it would be easier to read if the condition was included in the while() statement

Signature · 2 lines
Hardware, n.:
 The parts of a computer system that can be kicked.
author
#2 lore raw
Quoted 6 lines · Andrew Dyer

looking at how cache_flush() is used (see common/cmd_load.c, common/cmd_elf.c, etc), I believe this loop should also do a cache_op with Hit_Invalidate_I to invalidate the icache.

seems like it would be easier to read if the condition was included in the while() statement

Hm, then is this ok?

cpu/mips/cpu.c +22 -0
index 7559ac6..e59c9c9 100644
@@ -25,6 +25,17 @@
 #include <command.h>
 #include <asm/inca-ip.h>
 #include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+
+#define cache_op(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	cache	%0, %1					\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {

@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
+	unsigned long lsize = CFG_DCACHE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, start_addr);
+		cache_op(Hit_Invalidate_I, start_addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
 }
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
author
#3 lore raw
Quoted 9 lines · Shinya Kuribayashi
Quoted 6 lines · Andrew Dyer

looking at how cache_flush() is used (see common/cmd_load.c, common/cmd_elf.c, etc), I believe this loop should also do a cache_op with Hit_Invalidate_I to invalidate the icache.

seems like it would be easier to read if the condition was included in the while() statement

Hm, then is this ok?

<snip>

Review int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) · line 55

Quoted 5 lines
(quoted diff) +1 -0
@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
+	unsigned long lsize = CFG_DCACHE_SIZE;

                              ^^^^^^^^^^^^^^^

Oops, this should have been cache line size.

Patch updated.

P.S. I'll introduce <asm/r4kcache.h> and remove cache_op macro in the
future. But it takes some time.

================>

[MIPS] Implement flush_cache()

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cpu.c |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)
cpu/mips/cpu.c +22 -0
index 7559ac6..de70c4d 100644
@@ -25,6 +25,17 @@
 #include <command.h>
 #include <asm/inca-ip.h>
 #include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+
+#define cache_op(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	cache	%0, %1					\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {

@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
+	unsigned long lsize = CFG_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, start_addr);
+		cache_op(Hit_Invalidate_I, start_addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
 }
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)