mpc8323erdb: Improve the system performance
PATCH 2/3 mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting.
The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).Signed-off-by Michael Barkowski <[email protected]>
Acked-by Kim Phillips <[email protected]>
--- cpu/mpc83xx/cpu_init.c | 6 ++++++ include/configs/MPC8323ERDB.h | 35 +++++++++++++++++++++-------------- include/mpc83xx.h | 1 + 3 files changed, 28 insertions(+), 14 deletions(-)
cpu/mpc83xx/cpu_init.c +6 -0
@@ -79,6 +79,12 @@ void cpu_init_f (volatile immap_t * im) (CFG_ACR_RPTCNT <<ACR_RPTCNT_SHIFT );#endif +#ifdef CFG_SPCR_OPT +/* Optimize transactions between CSB and other devices */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT ) | + (CFG_SPCR_OPT <<SPCR_OPT_SHIFT ); +#endif +#ifdef CFG_SPCR_TSECEP /* all eTSEC's Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
include/configs/MPC8323ERDB.h +21 -14
@@ -66,6 +66,13 @@#define CFG_IMMR 0xE0000000/* +* System performance +*/ +#define CFG_ACR_PIPE_DEP 3/* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3/* Arbiter repeat count (0-7) */ +#define CFG_SPCR_OPT 1/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ + +/* * DDR Setup */ #define CFG_DDR_BASE 0x00000000/* DDR is system memory */
@@ -83,10 +90,9 @@*/ #define CFG_DDR_SIZE 64/* MB */ #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ - | CSCONFIG_AP \ - | 0x00040000 /* TODO */ \ + | CSCONFIG_ODT_WR_ACS \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) -/* 0x80840101 */ +/* 0x80010101 */ #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
@@ -96,28 +102,29 @@ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )/* 0x00220802 */ -#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ - | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ +#define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ - | (13 << TIMING_CFG1_REFREC_SHIFT ) \ - | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) -/* 0x3935d322 */ -#define CFG_DDR_TIMING_2 ( (31 << TIMING_CFG2_CPO_SHIFT ) \ +/* 0x26253222 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | (31 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) -/* 0x0f9048ca */ + | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) +/* 0x1f9048c7 */ #define CFG_DDR_TIMING_3 0x00000000#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05/* 0x02000000 */ -#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) -/* 0x44400232 */ +/* 0x44480232 */ #define CFG_DDR_MODE2 0x8000c000#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
include/mpc83xx.h +1 -0
@@ -121,6 +121,7 @@#define SPCR_PCIPR 0x03000000/* PCI bridge system bus request priority */ #define SPCR_PCIPR_SHIFT (31-7)#define SPCR_OPT 0x00800000/* Optimize */ +#define SPCR_OPT_SHIFT (31-8)#define SPCR_TBEN 0x00400000/* E300 PowerPC core time base unit enable */ #define SPCR_TBEN_SHIFT (31-9)#define SPCR_COREPR 0x00300000/* E300 PowerPC Core system bus request priority */
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1.5.3.6