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Extend MIPS_MAX_CACHE_SIZE upto 64kB

U-Boot-Users Shinya Kuribayashi 1 participant 2 messages Mar 23, 2008 – Mar 25, 2008

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Shinya Kuribayashi

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#0 lore raw
Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cache.S |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)
cpu/mips/cache.S +5 -4
index bda9bb1..2998a3b 100644
@@ -32,10 +32,11 @@
 
 #define RA		t8
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.
-	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, 34K, etc. Set bigger size for convenience.
+ */
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 #define INDEX_BASE	KSEG0
author
#1 lore raw
Quoted 17 lines · Shinya Kuribayashi
Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cache.S |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)
cpu/mips/cache.S +0 -2
index bda9bb1..2998a3b 100644
@@ -32,10 +32,11 @@
 
 #define RA		t8
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.

cpu/mips/cache.S line 42

Quoted 10 lines
cpu/mips/cache.S +5 -2
-	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, 34K, etc. Set bigger size for convenience.
+ */
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 #define INDEX_BASE	KSEG0

Revised patch is attached.

- add some comments on L2 cache,
- and cache.S is no longer 4K specific routines now!

================>

[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB

From: Shinya Kuribayashi <[email protected]>

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 cpu/mips/cache.S |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)
cpu/mips/cache.S +9 -5
index e6f3175..89ada71 100644
@@ -1,5 +1,5 @@
 /*
- *  Cache-handling routined for MIPS 4K CPUs
+ *  Cache-handling routined for MIPS CPUs
  *
  *  Copyright (c) 2003	Wolfgang Denk <[email protected]>
  *

@@ -32,10 +32,14 @@
 
 #define RA		t8
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.
-	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 #define INDEX_BASE	KSEG0