add MPC8343 based board mvBlueLYNX-M7

+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */

(quoted diff) +40 -0

+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+	0
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C20_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+		gd->reloc_off);
+	fpga_init(gd->reloc_off);
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}

(quoted diff) +39 -0

+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->dat & FPGA_CONF_DONE)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->dat & FPGA_STATUS)  {
+		fpga_debug("high\n");
+		result = 1;

(quoted diff) +37 -0

+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "mvblm7.h"
+
+int fixed_sdram(void)

(quoted diff) +42 -0

+		if (ddr_size & 1)
+			return -1;
+	}
+	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+		LAWAR_SIZE);
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* DHCP_CLIENT_IDENTIFIER = 61 */
+	ptr = getenv("dhcp_client_id");
+	if (ptr) {
+		*e++ = 61;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+	return fpga_load(0, fpga_data, data_size);
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CFG_PCI1_MEM_BASE,
+		phys_start: CFG_PCI1_MEM_PHYS,
+		size: CFG_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CFG_PCI1_MMIO_BASE,
+		phys_start: CFG_PCI1_MMIO_PHYS,
+		size: CFG_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CFG_PCI1_IO_BASE,

Quoted 22 lines

+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */

Review

Quoted 8 lines

(quoted diff) +8 -0

+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvblm7.h"
+
+#ifdef CONFIG_FPGA

Please move it to the Makefile

Quoted 41 lines

(quoted diff) +40 -0

+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+	0
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	passive_serial,
+	Altera_EP2C20_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+	fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+		gd->reloc_off);
+	fpga_init(gd->reloc_off);
+	fpga_add(fpga_altera, &cyclone2);
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return 1;
+}

Review

Quoted 10 lines

(quoted diff) +10 -0

+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];

please remove empty line

Review

Quoted 3 lines

(quoted diff) +2 -0

+
+	u32 dvo = gpio->dat;

please add empty line

Quoted 40 lines

(quoted diff) +39 -0

+	fpga_debug("SET config : %s\n", assert ? "low" : "high");
+	if (assert)
+		dvo |= FPGA_CONFIG;
+	else
+		dvo &= ~FPGA_CONFIG;
+
+	if (flush)
+		gpio->dat = dvo;
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	udelay(10);
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio->dat & FPGA_CONF_DONE)  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+	int result = 0;
+
+	fpga_debug("STATUS check ... ");
+	if (gpio->dat & FPGA_STATUS)  {
+		fpga_debug("high\n");
+		result = 1;

Review

Quoted 10 lines

(quoted diff) +10 -0

+	} else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];

please remove empty line

Review

Quoted 3 lines

(quoted diff) +2 -0

+
+	u32 dvo = gpio->dat;

please add empty line

Quoted 38 lines

(quoted diff) +37 -0

+	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+	if (assert_clk)
+		dvo |= FPGA_CCLK;
+	else
+		dvo &= ~FPGA_CCLK;
+
+	if (flush)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "mvblm7.h"
+
+int fixed_sdram(void)

Review

Quoted 10 lines

(quoted diff) +10 -0

+{
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+		(ddr_size > 1);
+		ddr_size = ddr_size>>1, ddr_size_log2++) {

                                  ^  ^

please add space

Quoted 43 lines

(quoted diff) +42 -0

+		if (ddr_size & 1)
+			return -1;
+	}
+	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+		LAWAR_SIZE);
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* DHCP_CLIENT_IDENTIFIER = 61 */
+	ptr = getenv("dhcp_client_id");
+	if (ptr) {
+		*e++ = 61;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+	return fpga_load(0, fpga_data, data_size);
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CFG_PCI1_MEM_BASE,
+		phys_start: CFG_PCI1_MEM_PHYS,
+		size: CFG_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CFG_PCI1_MMIO_BASE,
+		phys_start: CFG_PCI1_MMIO_PHYS,
+		size: CFG_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CFG_PCI1_IO_BASE,

Review

Quoted 10 lines

(quoted diff) +10 -0

+		phys_start: CFG_PCI1_IO_PHYS,
+		size: CFG_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	char *s;
+	int i, warmboot, load_fpga=0;

Please split it

Review

Quoted 2 lines

(quoted diff) +1 -0

+	volatile immap_t *immr;

Best Regards,
J.

I'll re-send the 23rd try after my vacation at end of may. If the merge window will be closed at that date it's obviously bad luck.

Quoted 2 lines · On Wed, 07 May 2008 12:01:48 +0200 Andr? Schwarz…

I'll re-send the 23rd try after my vacation at end of may. If the merge window will be closed at that date it's obviously bad luck.

I can make the changes, Andr?, thanks!

This is a multi-part message in MIME format.
--------------050700010403060204060205
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit

Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.

Signed-off-by Andre Schwarz <[email protected]>

Quoted 9 lines · On Wed, 7 May 2008 10:36:56 -0500 Kim Phillips <[email protected]>…

Quoted 3 lines · On Wed, 07 May 2008 12:01:48 +0200 Andr?? Schwarz…

I'll re-send the 23rd try after my vacation at end of may. If the merge window will be closed at that date it's obviously bad luck.

I can make the changes, Andr??, thanks!

hmm..made the below changes, but I don't know how to recover from:

fpga.c:55: error: ???Altera_EP2C20_SIZE??? undeclared here (not in a function)

it seems this never built? also, we are missing a config file in the latest submission. One more thing: please submit patches in an order that will not break future builds during a git-bisect session, i.e., since I believe a single patch is less than the ML limit of 40KB, make it a single patch, please.

Thanks,

Kim

board/mvblm7/Makefile +4 -1

index 84cd14a..42e0243 100644
@@ -24,8 +24,11 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o pci.o fpga.o
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_FPGA) += fpga.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/mvblm7/fpga.c +2 -5

index 5eaa037..a60af01 100644
@@ -32,8 +32,6 @@
 #include "fpga.h"
 #include "mvblm7.h"
 
-#ifdef CONFIG_FPGA
-
 #ifdef FPGA_DEBUG
 #define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
 #else

@@ -83,8 +81,8 @@ int fpga_config_fn(int assert, int flush, int cookie)
 {
 	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-
 	u32 dvo = gpio->dat;
+
 	fpga_debug("SET config : %s\n", assert ? "low" : "high");
 	if (assert)
 		dvo |= FPGA_CONFIG;

@@ -134,8 +132,8 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie)
 {
 	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-
 	u32 dvo = gpio->dat;
+
 	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
 	if (assert_clk)
 		dvo |= FPGA_CCLK;

@@ -188,4 +186,3 @@ int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
 
 	return FPGA_SUCCESS;
 }
-#endif

board/mvblm7/mvblm7.c +4 -6

index 8f8e299..7e9b71f 100644
@@ -43,15 +43,14 @@ int fixed_sdram(void)
 	u32 ddr_size_log2;
 
 	msize = CFG_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-		(ddr_size > 1);
-		ddr_size = ddr_size>>1, ddr_size_log2++) {
+	for (ddr_size = msize << 20, ddr_size_log2 = 0; ddr_size > 1;
+		ddr_size = ddr_size >> 1, ddr_size_log2++)
 		if (ddr_size & 1)
 			return -1;
-	}
+
 	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
-		LAWAR_SIZE);
+					       LAWAR_SIZE);
 
 	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
 	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;

@@ -131,5 +130,4 @@ void ft_board_setup(void *blob, bd_t *bd)
 	ft_pci_setup(blob, bd);
 #endif
 }
-
 #endif

board/mvblm7/pci.c +3 -1

index b6453d0..72123c8 100644
@@ -28,11 +28,14 @@
 #include <libfdt.h>
 #endif
 #include <pci.h>
+#include <fpga.h>
 #include <mpc83xx.h>
 #include "mvblm7.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern int mvblm7_init_fpga(void);
+
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
 
-------------------------------------------------------------------------

This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2.
http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone
_______________________________________________
U-Boot-Users mailing list
U-Boot-Users at lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/u-boot-users

Do you want me to re-send a complete set of patches for the M7-Board against the latest version ?