Fix asm constraints for 'ins' instructions.

PATCH New David Daney 1 participant 1 message May 27, 2008 MIPS

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David Daney

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2008-05-27 07:04 UTC #0 lore raw

PATCH 1/1 Fix asm constraints for 'ins' instructions.

The third operand to 'ins' must be a constant int, not a register.

Signed-off-by David Daney <[email protected]>

---
 include/asm-mips/bitops.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

include/asm-mips/bitops.h +3 -3

index 6427247..9a7274b 100644
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 		"2:	b	1b					\n"
 		"	.previous					\n"
 		: "=&r" (temp), "=m" (*m)
-		: "ir" (bit), "m" (*m), "r" (~0));
+		: "i" (bit), "m" (*m), "r" (~0));
 #endif /* CONFIG_CPU_MIPSR2 */
 	} else if (cpu_has_llsc) {
 		__asm__ __volatile__(

@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 		"2:	b	1b					\n"
 		"	.previous					\n"
 		: "=&r" (temp), "=m" (*m)
-		: "ir" (bit), "m" (*m));
+		: "i" (bit), "m" (*m));
 #endif /* CONFIG_CPU_MIPSR2 */
 	} else if (cpu_has_llsc) {
 		__asm__ __volatile__(

@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 		"2:	b	1b					\n"
 		"	.previous					\n"
 		: "=&r" (temp), "=m" (*m), "=&r" (res)
-		: "ri" (bit), "m" (*m)
+		: "i" (bit), "m" (*m)
 		: "memory");
 #endif
 	} else if (cpu_has_llsc) {

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